In this role, you will work on leading-edge packaging technologies to enable AI architectures that will set new industry standards regarding compute power, performance, and efficiency.

You will collaborate with the packaging team to carry out the required structural analysis for packaging technologies under consideration, identify key failure modes under product use conditions, and run appropriate parametric studies to influence product and package design upstream. You will focus on thermo-mechanical analysis and characterization of advanced photonics packaging technologies, including 3D stack development, heterogeneous integration of lasers and novel fiber attach methods, to define design, material, and process solutions that successfully meet assembly and reliability requirements. The results of your work will lead to advanced package designs that meet power dissipation, optical, assembly, and reliability requirements while delivering a system-level solution for leading-edge products in the AI market.

Responsibilities: 

• Serve as the technical authority for thermo-mechanical simulation within the packaging organization, setting standards for model fidelity, validation methodology, and documentation practices adopted across the team.
• Identify capability gaps in simulation tooling, characterization methods, or material databases and champion fundamental investigations that strengthen the team's long-term technical foundation.
• Develop finite element stress, warpage, and assembly process models for wafer-level and unit-level photonic packaging, identifying design, process, and material parameters to mitigate failure modes and optimize yield.
• Perform analysis to identify key reliability risks under product use conditions and drive appropriate design and material solutions to improve product mechanical integrity.
• Conduct multi-physics simulations including solder collapse modeling for bump architecture definition and thermal-structural analysis for packaging stress to meet thermal, electrical, and optical requirements.
• Develop analytical or semi-empirical models for quick turn assessments for new product concepts.
• Drive characterization and validation of mechanical designs and electronic assemblies through lab-scale prototyping and vendor-initiated experiments, closing the loop between simulation predictions and physical hardware.
• Develop Python and MATLAB automation frameworks to scale simulation throughput and establish repeatable, high-efficiency modeling workflows.
• Summarize and communicate findings and recommendations with authority to key stakeholders across Lightmatter, suppliers, and customers.
• Write reports and document methodologies that serve as the technical foundation for the packaging team.

Required Qualifications:

• MS or PhD in Mechanical Engineering, Material Science, or a related engineering field.
• Deep expertise in finite element analysis using commercial tools such as Ansys, Abaqus, or equivalent, with demonstrated ability to develop and validate models for complex multi-material assemblies.
• Hands-on experience with multi-physics simulation including thermal-structural coupling, solder joint fatigue modeling, and warpage analysis.
• Strong understanding of semiconductor packaging failure modes including solder fatigue, delamination, CTE mismatch-driven stress, and underfill cracking under thermal cycling conditions.
• Experience with wafer-level and unit-level assembly processes including flip-chip, BGA, and advanced 3D packaging architectures.
• Proficiency in Python and/or MATLAB for simulation automation, data analysis, and scripting.
• Demonstrated ability to develop analytical or semi-empirical models for first-order engineering assessments.
• Experience driving characterization and validation programs through internal prototyping and external vendor collaboration.

Preferred Qualifications: 

• Proven track record of communicating complex technical findings to cross-functional audiences including design, process, and product engineering teams.
• Strong technical writing skills with experience producing simulation reports, design guidelines, and methodology documentation.
• Experience with photonic packaging technologies including silicon photonics, co-packaged optics, fiber attach, or heterogeneous integration of laser devices.
• Familiarity with optical packaging reliability requirements and the intersection of thermo-mechanical performance with optical alignment stability.
• Ability to work independently and manage multiple projects with minimal supervision.
• Experience with statistical analysis tools and techniques such as DOE and JMP.
• Strong creative thinking skills with the ability to solve problems quickly.

We are hiring a Chip Firmware Validation Engineer to help us build the next generation of photonic AI processors and interconnects.

In this role, you will be responsible for developing and validating the device software and firmware stack for Photonic Compute and Photonic Interconnect products. You will collaborate with other software and hardware systems teams to develop firmware, conduct validation and reliability testing, perform data analysis, and execute further software stack optimization.

Join a tight-knit team where each individual’s contributions directly impact the success of the company and our innovative products. At Lightmatter, you’ll have the opportunity to work with people who love to build and who thrive in technically diverse environments where great ideas are valued and prioritized.

Responsibilities

• Collaborate across a multidisciplinary team including photonics, analog, digital, systems, and network experts to define the control architecture for Lightmatter's photonic interconnect products.
• Drive the software and firmware validation testing for our photonic products.
• Debug and troubleshoot embedded systems using tools such as GDB, JTAG, and logic analyzers.
• Participate in defining product architecture and validation test plans definition to gather requirements and usability criteria.

Qualifications

• BS in Electrical Engineering, Computer Science, or a related field with 5+ years of experience in ASIC firmware validation.
• Strong understanding of hardware-software integration.
• Practical knowledge of communication and control in embedded systems, peripherals, and buses.
• Experience in embedded software development.
• Experience developing commercial or enterprise-level software and firmware on Linux.
• Experience with Git and CMake for building and managing software projects.
• Hands-on experience with data gathering, analysis, and reporting.
• Proficiency with Python, C, C++ and MongoDB.

Preferred Qualifications:

• Experience with Snowflake reporting software
• Experience with environments such as CMIS and OpenBMC, and familiarity with validation and reliability/FIT(Failure in Time) testing.
• Familiarity with optical test, measurement and methodologies for characterizing optical components and systems.
• Experience developing firmware for photonic transceivers or similar systems.

About this Role

In this role, you will contribute to the development of board and system solutions that leverage Lightmatter's technology to enable advanced machine learning, artificial intelligence, and large-scale interconnect platforms. You will collaborate closely with teams across hardware and software to design, bring up, and validate system-level products.

Responsibilities

• Design and develop power, control, mixed-signal, and high-speed interconnect circuits to meet system requirements
• Apply SI/PI, DfX, and industry best practices to meet performance and quality needs
• Perform board bring-up, verification, integration, and troubleshooting
• Develop and execute test plans to characterize and validate board and system performance
• Collaborate with cross-functional teams from concept design through integration and production
• Work with component vendors, contract manufacturers, and other partners
• Research new components, processes, and technologies to meet product goals
• Contribute to design reviews and maintain documentation including design notes, test reports, and specifications

Qualifications

• Bachelor's Degree in Electrical Engineering and 5+ years of related experience; or Master's Degree with 3+ years of related experience
• Proficient in schematic design using Altium or equivalent (Altium preferred)
• Experience performing lab experiments, board bring-up, tests, and analysis
• Familiarity with Product Lifecycle Management processes and tools (Arena preferred)

Preferred Qualifications

• Familiarity with electrical systems in the networking or similar industries
• Experience with common design, manufacturing, and test processes
• Experience with cross-functional development and troubleshooting
• Familiarity with signal integrity (SI), power integrity (PI), and DfX considerations
• Experience with high-speed interfaces such as PCIe, DDR, Ethernet, or SerDes
• Experience with Python or scripting languages for test automation and lab tooling

We are hiring a Photonics Design Engineer to join our development team. In this role, you will design, layout, and test silicon photonics devices for an integrated and scalable laser system.You will collaborate closely with cross-functional teams including photonics, packaging, systems, and software to define and refine specifications, ensuring that all designs meet or exceed performance targets and align with product requirements.

Join a tight-knit team where each individual’s contributions directly influence the success of the company and product. You'll have the opportunity to build innovative laser solutions from the ground up and tackle groundbreaking challenges. Work with people who love to build and who thrive in diverse technical environments where great ideas are prioritized.

Key Responsibilities:

• Design and optimize silicon photonic devices for laser systems, including couplers, muxes, rings, switches, and other active and passive components.
• Layout device test structures as well as complex integrated photonic systems.
• Work with the characterization team to develop and execute test plans for device validation, analyzing results to assess performance and troubleshoot issues.
• Work closely with packaging and systems engineering teams to address integration challenges, ensuring high alignment between device and system requirements.
• Implement rigorous simulation, modeling, and testing methodologies to calibrate designs and optimize performance across manufacturing variability.
• Engage in problem solving and contribute to new device designs and architectures.
• Publish novel photonics results, and participate in premier optics/photonics conferences.

Required Qualifications:

• PhD in Electrical Engineering, Physics, Photonics, or related discipline with 3 years of industry experience
• Experience in silicon photonics device design, layout, and testing, ideally in a product development environment
• Demonstrated track record of designing integrated silicon photonics components using Lumerical, Tidy3D, or equivalent
• Proficiency in modeling and data analysis in Python
• Experience with integrated lasers, SOAs
• Excellent communication skills, with a demonstrated ability to collaborate effectively with multidisciplinary teams
• Demonstrate strong problem solving skills in problems that do not have obvious solutions
• Can-do, positive attitude

Preferred Qualifications:

• Experience doing layout with foundry PDKs
• Experience with code-based GDS creation such as GDS Factory or similar
• Experience with optical and electronic test equipment, wafer-level testing and statistical data analysis (e.g., optical spectrum analyzers, tunable lasers, OBR/OVA, oscilloscopes, BERT).
• Strong project execution skills, with the ability to handle multiple priorities and meet project milestones.

We are hiring a Sr Technical Program Manager (TPM) to drive program execution across Lightmatter's Hardware Systems team. You will drive schedules, resource planning, priorities, and cross-functional alignment for all projects and activities within the team - spanning electrical, mechanical, and system engineering.. You will work closely with internal teams such as SI, PI, SW, supply chain, and with external partners, including contract manufacturers, PCB and sheet metal fabricators, assembly houses, and other suppliers, to keep programs on track from early design through production.

In this role, you will manage dependencies and trade-offs across concurrent workstreams, facilitate alignment across internal and external stakeholders, and maintain program visibility for engineering leadership. Your scope covers the full hardware development lifecycle, from design through production, including the engineering support programs, test infrastructure, and tooling that keep the broader team moving. You will also serve as the team's primary program interface to broader organizational programs, ensuring that schedule changes, material commitments, and engineering status are communicated accurately and on time to cross-functional program stakeholders.

This is a hands-on role that combines strong program management fundamentals with a working knowledge of hardware engineering. You will be equally at home in a design review, a supplier call, a resource planning discussion, and an executive status update. You will also need to thrive in a fast-moving environment where requirements evolve, priorities shift, and not every process is fully established, and bring the clarity and structure that turns that ambiguity into forward progress.

Responsibilities

• Own program coordination across all HW Systems activities: maintain an integrated schedule across all concurrent projects and workstreams, surface priority conflicts, and drive resolution of resource contention with engineering leads.
• Drive cross-functional alignment between HW Systems and other teams: setting agendas, facilitating meetings, capturing decisions, communicating delays and risks, and relentlessly following up on action items
• Manage team-wide resource loading and capacity visibility, partnering with engineering leads to flag overallocation risks and drive trade-offs discussions across concurrent programs
• Build and maintain integrated program schedules that reflect hardware development realities - bring-up milestones, NPI phases, EVT/DVT/PVT gates, and cross-team dependencies
• Own program scope that lives outside formal project charters: tester boards, demos, lab fixtures, calibration equipment, and internal engineering tools that teams depend on but that would otherwise lack dedicated ownership
• Coordinate material flow within the HW Systems team: track component orders, PCB fab runs, PCBA and mechanical assemblies, and engineering samples; partner with supply chain to ensure critical materials land on schedule
• Track and coordinate cross-functional teams' HW deliverable dependencies including quantities and timelines, and ensure downstream teams are unblocked with accurate, up-to-date visibility into HW schedule and status 
• Serve as the primary hardware program interface with external contract manufacturers, PCB and sheet metal fabricators, and assembly houses: managing schedules, tracking deliverables, facilitating technical alignment, and driving closure on open issues in partnership with Supply chain.
• Represent the HW Systems team in company-wide program reviews and cross-functional planning cadences; own the team's program interface to broader organizational stakeholders, communicating schedule changes, material needs, and engineering commitments proactively and clearly
• Track HW Systems budgets for engineering activities, prototype builds, and tooling; coordinate with finance and operations to ensure spend is planned, visible, and aligned with program milestones
• Adapt quickly to change: replan and realign when scope shifts, schedules move, or engineering realities force a pivot; maintain momentum and clarity even when the path forward is not fully defined
• Establish and maintain lightweight program management processes: status reporting cadences, risk registers, dependency tracking, and decision logs

Qualifications

• Bachelor’s degree in Engineering or a related technical field.
• 5+ years of program management experience in hardware engineering, with direct exposure to electrical and mechanical development cycles.
• Proven track record managing concurrent engineering programs with shared resources and overlapping timelines.
• Deep familiarity with hardware development processes and terminology across the full lifecycle—including PCBA and mechanical enclosures, PCB fabrication, system integration, bring-up, EVT/DVT/PVT, and production—enabling clear communication with engineers and vendors.
• Proven experience coordinating with contract manufacturers (CMs) and ODMs to manage schedules, track deliverables, and resolve open issues.
• Hands-on experience with material flow, component tracking, and BOM management.
• Skilled facilitator who drives productive meetings, captures critical context, and ensures action items are owned and closed.
• Strong written and verbal communicator, comfortable presenting program status and risk assessments to engineering leads and executives.
• Expert in project management tools such as Microsoft Project, Jira, Smartsheet, or equivalent platforms.
• Strong bias for action—consistently closes loops, follows up independently, and identifies potential slips before they impact project timelines.
• Thrives in fast-paced, ambiguous environments; proactively creates structure and drives clarity without waiting for complete information.

Preferred Qualifications

• Experience managing programs for complex hardware development
• Experience defining and improving program management processes in a startup or new business unit

This role is open to two different levels.

Staff: $189,000 - $210,000

Sr Staff: $217,000 - $252,000

We are hiring a Sr Technical Program Manager (TPM) to drive program execution across Lightmatter's Hardware Systems team. You will drive schedules, resource planning, priorities, and cross-functional alignment for all projects and activities within the team - spanning electrical, mechanical, and system engineering.. You will work closely with internal teams such as SI, PI, SW, supply chain, and with external partners, including contract manufacturers, PCB and sheet metal fabricators, assembly houses, and other suppliers, to keep programs on track from early design through production.

In this role, you will manage dependencies and trade-offs across concurrent workstreams, facilitate alignment across internal and external stakeholders, and maintain program visibility for engineering leadership. Your scope covers the full hardware development lifecycle, from design through production, including the engineering support programs, test infrastructure, and tooling that keep the broader team moving. You will also serve as the team's primary program interface to broader organizational programs, ensuring that schedule changes, material commitments, and engineering status are communicated accurately and on time to cross-functional program stakeholders.

This is a hands-on role that combines strong program management fundamentals with a working knowledge of hardware engineering. You will be equally at home in a design review, a supplier call, a resource planning discussion, and an executive status update. You will also need to thrive in a fast-moving environment where requirements evolve, priorities shift, and not every process is fully established, and bring the clarity and structure that turns that ambiguity into forward progress.

Responsibilities

• Own program coordination across all HW Systems activities: maintain an integrated schedule across all concurrent projects and workstreams, surface priority conflicts, and drive resolution of resource contention with engineering leads.
• Drive cross-functional alignment between HW Systems and other teams: setting agendas, facilitating meetings, capturing decisions, communicating delays and risks, and relentlessly following up on action items
• Manage team-wide resource loading and capacity visibility, partnering with engineering leads to flag overallocation risks and drive trade-offs discussions across concurrent programs
• Build and maintain integrated program schedules that reflect hardware development realities - bring-up milestones, NPI phases, EVT/DVT/PVT gates, and cross-team dependencies
• Own program scope that lives outside formal project charters: tester boards, demos, lab fixtures, calibration equipment, and internal engineering tools that teams depend on but that would otherwise lack dedicated ownership
• Coordinate material flow within the HW Systems team: track component orders, PCB fab runs, PCBA and mechanical assemblies, and engineering samples; partner with supply chain to ensure critical materials land on schedule
• Track and coordinate cross-functional teams' HW deliverable dependencies including quantities and timelines, and ensure downstream teams are unblocked with accurate, up-to-date visibility into HW schedule and status 
• Serve as the primary hardware program interface with external contract manufacturers, PCB and sheet metal fabricators, and assembly houses: managing schedules, tracking deliverables, facilitating technical alignment, and driving closure on open issues in partnership with Supply chain.
• Represent the HW Systems team in company-wide program reviews and cross-functional planning cadences; own the team's program interface to broader organizational stakeholders, communicating schedule changes, material needs, and engineering commitments proactively and clearly
• Track HW Systems budgets for engineering activities, prototype builds, and tooling; coordinate with finance and operations to ensure spend is planned, visible, and aligned with program milestones
• Adapt quickly to change: replan and realign when scope shifts, schedules move, or engineering realities force a pivot; maintain momentum and clarity even when the path forward is not fully defined
• Establish and maintain lightweight program management processes: status reporting cadences, risk registers, dependency tracking, and decision logs

Qualifications

• Bachelor’s degree in Engineering or a related technical field.
• 5+ years of program management experience in hardware engineering, with direct exposure to electrical and mechanical development cycles.
• Proven track record managing concurrent engineering programs with shared resources and overlapping timelines.
• Deep familiarity with hardware development processes and terminology across the full lifecycle—including PCBA and mechanical enclosures, PCB fabrication, system integration, bring-up, EVT/DVT/PVT, and production—enabling clear communication with engineers and vendors.
• Proven experience coordinating with contract manufacturers (CMs) and ODMs to manage schedules, track deliverables, and resolve open issues.
• Hands-on experience with material flow, component tracking, and BOM management.
• Skilled facilitator who drives productive meetings, captures critical context, and ensures action items are owned and closed.
• Strong written and verbal communicator, comfortable presenting program status and risk assessments to engineering leads and executives.
• Expert in project management tools such as Microsoft Project, Jira, Smartsheet, or equivalent platforms.
• Strong bias for action—consistently closes loops, follows up independently, and identifies potential slips before they impact project timelines.
• Thrives in fast-paced, ambiguous environments; proactively creates structure and drives clarity without waiting for complete information.

Preferred Qualifications

• Experience managing programs for complex hardware development
• Experience defining and improving program management processes in a startup or new business unit

This role is open to two different levels.

Staff: $171,000 - $200,000

Sr Staff: $203,000 - $243,000

In this role you will be responsible for designing, executing, and analyzing reliability tests to verify product performance, durability, and compliance with standards. You will enable our products to meet or exceed reliability requirements throughout their lifecycle by developing robust test protocols, analyzing failures, and working with cross-functional teams to drive improvements in design and manufacturing processes.

Responsibilities

• Develop reliability test plans based on product requirements, industry standards, and customer expectations.
• Execute reliability qualification testing for our highly integrated photonics-based AI platform and our photonics chiplet communication fabric products.
• Conduct Failure Modes and Effects Analysis (FMEA) to identify and mitigate potential reliability risks in device design and manufacturing.
• Perform detailed root cause analysis of device failures, and collaborate with cross-functional teams to resolve reliability issues, refine product designs, and improve process robustness.
• Establish internal reliability guidelines and standards to meet customer requirements and industry benchmarks.
• Utilize statistical analysis tools to model reliability performance and predict device lifetimes under field conditions.
• Prepare and present detailed technical reports, including reliability test plans, results, and risk assessments, to internal and external stakeholders.

Qualifications 

• Bachelor's degree in Electrical Engineering, Computer Engineering or a similar field
• 5+ years of industry experience working as a Reliability Engineer within the semiconductor and/or photonics industry.
• Understanding of device and package reliability testing methodologies, including HTOL, HAST, TDDB, HTHH, TC etc.
• Hands-on experience with failure analysis tools and techniques such as SEM, TEM, FIB, and EMMI etc.
• Knowledge of device physics, reliability and failure mechanism in Serdes/digital/mixed signal IC’s.
• Good understanding of packaging failure mechanisms and risks on TSV, solder joints, warpage, metal migrations etc.
• Familiarity with reliability modeling tools and statistical analysis (e.g., Weibull analysis, Minitab, JMP).

Preferred Qualification:

• Preferably experienced in semiconductor or photonics device/module testing.
• Experience with advanced packaging technologies such as flip-chip, wafer-level packaging, or 3D integration.
• Good statistical data analysis skills to analyze pre vs post reliability data.
• Excellent communication and presentation skills, with the ability to convey complex reliability concepts to diverse audiences.
• PhD in Electrical Engineering, Computer Engineering or a similar field , working as a Reliability Engineer for at least 1 year

 As a Design for Test Engineer you will work closely with all disciplines involved in chip design and product operations to design, validate, and deploy test solutions for digital, analog, and photonic logic. You will be involved in a variety of tasks including logic design, validation and logic simulations, scripting, timing closure, post-silicon planning and bring up, and bringing products to market.

Responsibilities

• Create new chip, module, and system-level DFT solutions for our highly integrated photonics-based AI platform
• Develop and deploy DFT methodologies for our next generation products
• Provide architecture for integrated electronics/analog/digital test including ATPG and boundary scan
• Work with RTL designers to define front-end integration
• Work with physical-design engineers to provide backend integration
• Create automated flow that can scale with the team and company
• Support initial silicon bring-up through debug 
• Validate DFT implementation and requirements
• Proactively solve problems while managing deliverables in a fast-paced, evolving environment.

Minimum Qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field
• At least 5 years of industry experience working on DFT-related activities for advanced ASIC designs
• Proven experience in pre-silicon design activities
• Work independently on daily tasks and projects, while seeking guidance for new and unfamiliar assignments.
• Experience with scripting languages such as Python or TCL
• Solid understanding of DFT concepts such as Scan, ATPG, memory test, and JTAG
• Knowledge of Basic SoC Architecture and HDL languages like Verilog
• Experience working with commercial EDA DFT tools on MBIST, ATPG, and Boundary Scan. 

Preferred Qualifications:

• Master degree in Electrical Engineering, Computer Engineering, or related field with 3+ years of industry experience working on ASIC designs with multiple production-quality ASIC tapeouts
• Prior experience working on DFT related tasks in either logic design, validation, implementation or pattern generation and coverage analysis
• Understanding of industry standards and practices in DFT, including JTAG/BSCAN, at-speed Scan-ATPG, MBIST, and trade-offs between test quality and test time
• Ability to conduct experiments during silicon debug, gathering and analyzing data, and utilize scripting to support efficient handling of ATE data 
• Understanding of Timing, Physical Design, and Power impact of DFT structures
• Strong teamwork and communication skills with the ability to collaborate with multiple functional teams across a variety of fields

 As a Design for Test Engineer you will work closely with all disciplines involved in chip design and product operations to design, validate, and deploy test solutions for digital, analog, and photonic logic. You will be involved in a variety of tasks including logic design, validation and logic simulations, scripting, timing closure, post-silicon planning and bring up, and bringing products to market.

Responsibilities

• Create new chip, module, and system-level DFT solutions for our highly integrated photonics-based AI platform
• Develop and deploy DFT methodologies for our next generation products
• Provide architecture for integrated electronics/analog/digital test including ATPG and boundary scan
• Work with RTL designers to define front-end integration
• Work with physical-design engineers to provide backend integration
• Create automated flow that can scale with the team and company
• Support initial silicon bring-up through debug 
• Validate DFT implementation and requirements
• Proactively solve problems while managing deliverables in a fast-paced, evolving environment.

Minimum Qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field
• At least 5 years of industry experience working on DFT-related activities for advanced ASIC designs
• Proven experience in pre-silicon design activities
• Work independently on daily tasks and projects, while seeking guidance for new and unfamiliar assignments.
• Experience with scripting languages such as Python or TCL
• Solid understanding of DFT concepts such as Scan, ATPG, memory test, and JTAG
• Knowledge of Basic SoC Architecture and HDL languages like Verilog
• Experience working with commercial EDA DFT tools on MBIST, ATPG, and Boundary Scan. 

Preferred Qualifications:

• Master degree in Electrical Engineering, Computer Engineering, or related field with 3+ years of industry experience working on ASIC designs with multiple production-quality ASIC tapeouts
• Prior experience working on DFT related tasks in either logic design, validation, implementation or pattern generation and coverage analysis
• Understanding of industry standards and practices in DFT, including JTAG/BSCAN, at-speed Scan-ATPG, MBIST, and trade-offs between test quality and test time
• Ability to conduct experiments during silicon debug, gathering and analyzing data, and utilize scripting to support efficient handling of ATE data 
• Understanding of Timing, Physical Design, and Power impact of DFT structures
• Strong teamwork and communication skills with the ability to collaborate with multiple functional teams across a variety of fields

We are hiring a Sr DFT Engineer to help us build high-performance ASICs for the next generation of AI acceleration systems. In this role, you will be responsible for physical design in leading-edge CMOS technology. This includes synthesis through place and route, timing closure, and tape-out signoff.

Responsibilities

• Perform Design For Test (DFT) insertion on ASIC designs, including internal scan, boundary scan, and memory BIST
• Perform automatic and targeted test pattern generation
• Interface with Physical Design and Front End (RTL) Design
• Perform post-silicon DFT bring-up and test program debug
• Interface with ATE engineers for test program bring-up and debug
• Scripting and automation of DFT and ATPG flow
• Be hands-on from the "nitty gritty" details to high level planning. 

Requirements

• Bachelor's degree in Electrical Engineering (or other related fields)
• Minimum of 13 years of industry experience working as a Design For Test Engineer on ASIC designs
• Must have completed at least 2 tapeouts
• Minimum of 2 years of experience with standard DFT CAD tools and flows
• Hands-on experience in Python, TCL or other scripting environments
• DFT/post-silicon/ATPG with experience in both ASIC and semi-custom COT flow
• Strong teamwork skills with the ability to collaborate with multiple functional teams across a variety of fields
• Ability to react to change and thrive in a fast paced environment

Preferred qualifications

• Masters degree in Electrical Engineering (or related fields) with 10+ years of DFT experience 
• Experience working on ASIC designs with multiple production-quality ASIC tapeouts
• Experience interfacing with ATE engineers
• Experience with ATE test program development
• Experience with fault modeling
• Understanding of Timing, Physical Design, and Power impact of DFT structures
• Proven Knowledge of Basic SoC Architecture and HDL languages like SystemVerilog and chipware components to work hand in hand with RTL designers