About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Center of Excellence (COE), part of the Custom Compute and Storage (CCS) Business Unit within Marvell's Data Center Group, is chartered to define, develop, and maintain standard, production-ready IP subsystems — spanning PCIe/CXL, Ethernet, DDR/Memory, Security/Boot, Low-Speed IO, and other critical technologies — that customers and internal SoC teams can adopt with confidence. By shifting left, the COE enables faster time-to-market, reduces integration risk, and ensures compliance, interoperability, and high performance across Marvell's SoC products. It embodies the "One Marvell" principle — sharing reusable components, verification environments, and knowledge across all business units to drive first-pass-right silicon. As part of the COE, you will design, verify, and deliver IP subsystem building blocks powering Marvell's most advanced custom chips for hyperscale cloud, AI, and data center customers — working at the intersection of architecture, RTL design, verification, firmware/software, and silicon validation. What You Can Expect Develop and execute verification plans for high-speed memory interfaces (PCIE 6/7, CXL 3.2/4.0) Build and enhance UVM/System Verilog-based verification environments Develop test benches, sequences, and checkers for functional and performance validation Perform protocol-level verification for PCIE controllers and PHY interfaces Analyze and debug simulation failures, identify root causes, and drive resolution Work closely with design, architecture, and firmware teams to ensure coverage closure and spec compliance Contribute to coverage-driven verification (CDV) including functional, code, and assertion coverage Support emulation/FPGA validation and post-silicon bring-up (nice to have) Review design specifications and provide feedback for testability and robustness Own end-to-end verification of PCIe (Gen6/Gen7) and CXL (3.0/4.0) subsystems, from test planning through coverage closure and signoff Define and execute comprehensive verification plans based on protocol specifications and micro-architecture requirements Architect and develop scalable UVM/System Verilog testbenches for PCIe/CXL controllers and fabric-level subsystems Integrate and configure PCIe/CXL VIP for subsystem and system-level verification environments Validate CXL.io, CXL.cache, and CXL.mem protocols, including coherency and memory semantics across complex flows Develop constrained-random and directed test suites to achieve high functional coverage across corner and stress scenarios Debug complex failures such as protocol violations, ordering issues, and coherency bugs using waveforms, logs, and protocol analyzers Implement System Verilog Assertions (SVA) for protocol compliance, improving early bug detection and debug efficiency Drive functional, code, and assertion coverage closure, identifying gaps and developing targeted tests to meet signoff goals Validate performance metrics (latency, throughput, QoS) under high-bandwidth and stress workloads Develop automation (Python/Shell) for regression management, log triage, and coverage reporting, improving productivity Collaborate with design, architecture, firmware and validation teams, influencing design-for-verification and mentoring junior engineers What We're Looking For Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or related field 5-10 years of experience in ASIC/SoC verification Strong knowledge of PCIE and CXL protocols and architecture Expertise in System Verilog and UVM methodology Experience with debugging complex verification issues Familiarity with industry-standard tools (e.g., simulation, waveform debugging, coverage tools) Solid understanding of digital design fundamentals Additional Preferred Requirements: Experience with assertion-based verification (SVA) Exposure to performance modeling and traffic generation Exposure to emulation platforms (e.g., Palladium, Veloce) a plus Scripting skills (Python/Perl/Shell) Experience with low-power verification (UPF) Expected Base Pay Range (USD) 135,900 - 201,130, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-AR3 Join our talent community to hear about company news, job openings and events. Join our Talent Community! Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Recruitment fraud is a well-known way that third parties try to get personal information or to steal money from you. Please review Marvell’s guidance here to learn more on how you can protect yourself.

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Center of Excellence (COE), part of the Custom Cloud Solutions (CCS) Business Unit within Marvell's Data Center Group, is chartered to define, develop, and maintain standard, production-ready IP subsystems — spanning PCIe/CXL, Ethernet, DDR/Memory, Security/Boot, Low-Speed IO, and other critical technologies — that customers and internal SoC teams can adopt with confidence. By shifting left, the COE enables faster time-to-market, reduces integration risk, and ensures compliance, interoperability, and high performance across Marvell's SoC products. It embodies the "One Marvell" principle — sharing reusable components, verification environments, and knowledge across all business units to drive first-pass-right silicon. As part of the COE, you will design, verify, and deliver IP subsystem building blocks powering Marvell's most advanced custom chips for hyperscale cloud, AI, and data center customers — working at the intersection of architecture, RTL design, verification, firmware/software, and silicon validation. What You Can Expect Own and drive DDR/LPDDR/HBM subsystem micro-architecture definition, RTL implementation, and integration Collaborate closely with Architecture teams to translate requirements into robust RTL designs Work with Design Verification teams on test-plan reviews, debug, and coverage closure Partner with Physical Design and DFT teams to ensure PD-friendly and DFT-ready RTL Support silicon bring-up and post-silicon debug, working with firmware and validation teams Drive design quality improvements, coding best practices, and reuse across projects Participate in design reviews, milestone reviews, and cross-functional technical discussions Mentor junior designers and provide technical leadership within the DDR/LPDDR/HBM design domain What We're Looking For Bachelor’s degree in Electronics/Electrical Engineering with 5-10+ years of relevant experience in RTL design or Master's and/or PhD with 3-5 yrs of relevant experience Proven experience delivering complex DDR, LPDDR, HBM controllers or subsystems from architecture through RTL closure Strong hands-on experience in System Verilog / Verilog RTL development Expertise/Familiarity in DDR/HBM JEDEC specifications Deep knowledge of ARM-based SoC integration and AMBA protocols (AXI-4, CHI, ACE) Solid grasp of Clocking, Resets, CDC/RDC, low-power techniques, and performance optimization Experience supporting lint, CDC/RDC, synthesis, and design sign-off flows Experience using industry-standard EDA tools from Synopsys, Cadence, Mentor/Siemens Proficient in scripting languages such as TCL / Perl / Python Experience with version control systems such as GIT, SVN, etc. Additional Qualifications: Experience on end-to-end DDR/HBM subsystem RTL design execution and sign-off Experience designing high-performance, low-latency data paths and handling ordering, coherency, and error mechanisms Proficient in debugging functional and performance issues at subsystem and SoC levels Familiarity with post-silicon bring-up and debug methodologies in collaboration with firmware and validation teams Prior experience mentoring engineers and providing technical leadership in a cross-functional environment Expected Base Pay Range (USD) 135,900 - 201,130, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-AR3 Join our talent community to hear about company news, job openings and events. Join our Talent Community! Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Recruitment fraud is a well-known way that third parties try to get personal information or to steal money from you. Please review Marvell’s guidance here to learn more on how you can protect yourself.

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell is expanding its global Test Solutions Engineering (TSE) organization and seeking an experienced Manager to establish, staff, and lead a new TSE team in the Santa Clara US region. The TSE organization owns ATE based production test development and plays a critical role in optimizing cost, quality, and NPI execution for Marvell’s custom data center silicon. This role has both organizational leadership responsibilities and deep technical ownership across new product introduction and high volume manufacturing readiness. You will be responsible for building the regional team, developing talent, driving execution, and partnering globally to support rapid production ramps for hyperscale customers. What You Can Expect Team Building & Organizational Leadership Build and scale the West Coast Test Solutions Engineering team, including hiring, onboarding, and developing engineering talent. Establish team structure, follow existing workflows, and technical best practices to support global TSE operations. Provide coaching, mentorship, performance management, and long‑term career development for the team. Foster a collaborative, high‑execution culture across regional and global teams. Program & Technical Leadership Lead end‑to‑end New Product Introduction (NPI) for assigned programs, from design start through production ramp. Own test strategy definition, architecture, and overall solution readiness for high‑volume manufacturing. Drive silicon bring‑up, debug, and characterization to validate production test coverage and performance. Ensure test solutions meet product requirements for quality, cost, and schedule. Customer & Cross‑Functional Engagement Serve as the primary technical and managerial interface to customers for test strategy alignment and issue resolution. Partner closely with design, DFT, product and test engineering, manufacturing operations, and quality teams across multiple regions. Quality, Reliability & Sustaining Engineering Support reliability qualifications, stress testing, and customer return analysis. Lead root‑cause analysis and drive corrective actions across engineering and manufacturing teams. Implement continuous improvement initiatives across test processes, yield, and test cost. What We're Looking For Required Qualifications Bachelor’s degree or higher in electrical engineering, Computer Engineering, Computer Science, or related field. 10-15 years of experience in Custom processor / ASIC Product Engineering, Test Engineering, DFT, or Technology Characterization. Demonstrated success managing or leading engineering teams, preferably across geographies. Strong understanding of: Product Engineering and Test Development Design‑for‑Test (DFT) Semiconductor devices and process technology Quality and reliability practices Proven ability to lead complex technical programs and drive cross‑functional alignment. Strong written and verbal communication skills. Preferred Qualifications Master’s or PhD in EE/CS (experience level dependent). Experience hiring and building new teams or leading organizational expansion. Experience supporting hyperscale or large enterprise customers. Experience working with global or distributed engineering teams. Expected Base Pay Range (USD) 185,390 - 277,700, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-TT1 Join our talent community to hear about company news, job openings and events. Join our Talent Community! Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Recruitment fraud is a well-known way that third parties try to get personal information or to steal money from you. Please review Marvell’s guidance here to learn more on how you can protect yourself.

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell’s Optical DSP (ODSP) team within the Connectivity Business Unit develops advanced, industry-leading ASICs for the hyperscale data center, enterprise, and AI infrastructure markets. Our products — including multi-terabit retimers, coherent DSP devices, and high-speed optical transceivers — are critical enablers for efficient, high-bandwidth data transmission across fiber optical networks and electrical interconnects at 100G+ per lane. The ODSP team operates at the leading edge of semiconductor technology, developing chips in TSMC advanced process nodes. We are a global, multi-site engineering organization spanning Santa Clara, Ottawa, Pavia, Irvine, Vietnam, and Argentina — and we are looking for a senior experienced technical leader to serve as Hardware Chip Lead on our next-generation ODSP programs. What You Can Expect Chip Ownership & Program Leadership · Serve as the primary hardware technical owner for an ODSP chip program, responsible for tracking and driving progress across all hardware design phases from POR (Plan of Record) through MPR (Mass Production) · Finalize the Product Requirements Document (PRD) and bring-up requirements in collaboration with architecture, marketing, and applications engineering teams · Represent hardware engineering at all key program milestones: Pre-PA, PA, PSM, POR, Design Reviews, Tape-Out, and MPR · Coordinate and align cross-functional teams including analog design, digital design, DV, DFT, physical design, STA, firmware, validation, ATE/test engineering, product engineering, and quality · Manage and communicate program status, risks, and mitigation plans to BU engineering leadership on a regular cadence Technical Leadership · Provide technical leadership for the full chip design, independently proposing and defining high-level technical solutions across the hardware stack · Set technical direction and drive resolution of complex, cross-disciplinary design challenges spanning analog/digital integration, high-speed SerDes, DSP datapath, and SoC architecture · Proactively identify technical risks early in the design cycle and drive mitigation strategies across functional teams · Take an active role in setting and prioritizing BU milestones and objectives; participate in architecture and design reviews at the chip and block level · Drive continuous improvement in design methodology, flows, and quality across the ODSP hardware organization Design & Execution · Lead end-to-end chip design execution across advanced CMOS nodes (TSMC 2nm/3nm/5nm), including architecture, RTL, physical design, DFT, timing closure, and tape-out · Own the chip bring-up plan and execution, coordinating multi-site teams across global locations; drive Phase 0, Phase 1, and Phase 2 bring-up activities through to silicon validation · Oversee silicon validation, PVT characterization, ATE test program development, qualification (ESD, LU, HTOL), and production release · Drive resolution of post-silicon issues, coordinating debug across analog, digital, firmware, and validation teams · Ensure all hardware deliverables — including PRD, design documentation, and bring-up requirements — are complete and on schedule Mentorship & Knowledge Sharing · Mentor and develop engineers across the ODSP hardware organization; invest in building technical depth and breadth within the team · Foster a culture of knowledge sharing, technical rigor, and continuous learning · Coach and develop engineering talent; provide guidance and feedback to support career growth at all levels What We're Looking For Education & Experience · Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field and 15+ years of related professional experience · OR Master’s degree in Electrical Engineering, Computer Engineering, or related field with 10–12 years of experience · OR PhD in Electrical Engineering, Computer Engineering, or related field with 8–10 years of experience Required Skills & Experience · Proven track record as a chip lead or equivalent technical owner on complex SoC/ASIC programs, from architecture through tape-out and post-silicon productization · Deep expertise in high-speed mixed-signal SoC design, including SerDes (100G+/lane), DSP datapath, analog/digital integration, and advanced CMOS process nodes (5nm, 3nm) · Strong understanding of the full ASIC design flow: micro-architecture, RTL, synthesis, DFT, physical design, STA, timing closure, and tape-out · Experience leading and coordinating cross-functional hardware teams across analog, digital, DV, DFT, PD, firmware, validation, and test engineering disciplines · Demonstrated ability to drive silicon bring-up, debug, and validation across multi-site global teams · Experience with ATE test program development, silicon characterization, qualification (HTOL, ESD, LU), and production release · Excellent communication, interpersonal, and presentation skills; ability to represent hardware engineering to BU leadership and cross-functional stakeholders · Highly motivated, self-driven, and able to manage ambiguity in a fast-paced, multi-program environment Preferred Skills · Familiarity with optical DSP, coherent or direct-detect transceiver architectures, or high-speed retimer products · Experience with eAVS (Adaptive Voltage Scaling) or similar power optimization subsystems · Knowledge of SiPho (Silicon Photonics) integration and module-level validation · Experience working in a multi-site, globally distributed engineering organization Expected Base Pay Range (USD) 182,360 - 273,200, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-TT1 Join our talent community to hear about company news, job openings and events. Join our Talent Community! Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Recruitment fraud is a well-known way that third parties try to get personal information or to steal money from you. Please review Marvell’s guidance here to learn more on how you can protect yourself.