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Hardware Engineer, FPGA
Normal Computing · New York City, New York, USA
Pay
$250k–340k
Setting
Hybrid
NORMAL COMPUTING | BUILD WITH US
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.
THE ROLE
Validating conventional silicon is a solved discipline. Validating silicon that computes with noise is not, and you will be the one who figures out how. As our FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early software development, and building the test infrastructure for post-silicon bring-up and characterization. Your scope spans the entire FPGA lifecycle: selecting hardware platforms, implementing complex RTL, debugging in the lab, and writing the software that drives it all, working daily with our silicon, EDA, and research teams.
WHAT YOU WILL OWN
- FPGA Platform Ownership: Lead the selection, procurement, and bring-up of FPGA prototyping platforms (e.g., HAPS, VCU118/VPK180-class boards, or custom hardware) for pre-silicon RTL validation and software development.
- RTL Implementation: Adapt and implement complex ASIC RTL onto FPGA targets, including multi-clock-domain architectures, CDC bridges, and timing closure on dense designs.
- IP Integration: Integrate in-house designs with third-party and vendor IP; serve as the expert on the AMD/Xilinx ecosystem (Vivado IP Integrator, transceivers, memory controllers).
- High-Speed Interfaces: Design, implement, and validate high-speed I/O with a focus on PCIe: our accelerators ship as PCIe cards in standard servers.
- Post-Silicon Validation: Build FPGA-based "tester" designs for silicon bring-up, device characterization, and automated test environments.
- Hardware-Software Stack: Develop the software layer around the hardware: Python/C++ hardware abstraction, register-map generation, and automated build and regression flows.
- Lab Debug: Root-cause complex timing and functional issues in real time using ILA/Vivado Analyzer, oscilloscopes, logic analyzers, and BER/eye-diagram characterization of high-speed links.
WHAT MAKES YOU A GREAT FIT
- Proven industry experience taking FPGA designs from RTL through timing closure to validated hardware, ideally in an ASIC prototyping, emulation, or high-growth hardware environment.
- Expert-level SystemVerilog and/or VHDL for synthesis, with deep proficiency in Xilinx Vivado (synthesis, place & route, timing closure, IP catalog).
- Hands-on experience implementing and debugging PCIe, plus AXI/AHB, SPI, UART, JTAG, and other common interfaces.
- Strong Python for automation, test, and build tooling.
- Strong board-level bring-up and lab debugging skills on real hardware.
- Startup mindset: you work independently, pivot quickly, and run at ambiguous problems that span hardware, software, and physics.
BONUS POINTS
- Verification frameworks like Cocotb or UVM
- Experience deploying ML models to FPGAs (hls4ml, FINN, or custom NN-to-RTL flows), or building real-time, sub-microsecond signal processing pipelines.
- Mixed-signal ASIC exposure: digital front-ends, ADC/DAC interfaces, or analog compute.
- SERDES tuning and signal integrity fundamentals.
- CI/CD for hardware (GitLab CI, Docker-based build and test).
Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.
Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.
Software Engineer, Backend
Normal Computing · New York City, New York, USA
Pay
$200k–400k
Setting
Hybrid
Infrastructure Software Engineer
Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.
AI Engineer
Normal Computing · New York City, New York, USA
Pay
$200k–400k
Setting
Hybrid
Staff AI Engineer
Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.
Design Verification Engineer
Normal Computing · New York City, New York, USA
Pay
$110k–205k
Setting
Hybrid
NORMAL COMPUTING | BUILD WITH US
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, San Francisco, London, Copenhagen, and Pangyo.
THE ROLE
As a Design Verification Engineer at Normal, you will verify our own physics-inspired ASICs on the road to tapeout, and set the quality bar for what our AI learns: reviewing generated verification collateral and shaping the standards our models train against. From time to time, you may also be tapped to support a customer deployment alongside our forward-deployed team, where your verification credibility helps our AI platform land inside real DV flows. The through-line is your DV expertise, applied to silicon that computes differently than anything you've verified before, and to the AI that is changing how verification gets done. This is a seat for a verification engineer who wants their craft to compound rather than repeat.
WHAT YOU WILL OWN
- Thermodynamic ASIC Verification: Own design verification for Normal's internal silicon: testbench environments, assertions, and coverage from design documents through functional coverage and closure, supporting the program to tapeout.
- AI Product Refinement: Review AI-generated verification collateral to shape product strategy and tool usability in collaboration with the ML and product teams.
- Data Quality Bar: Set the quality standard for verification training data: define rubrics, curate golden examples, and partner with our Data team, who own the pipelines, so our models learn from verification artifacts a real DV engineer would sign off on.
- Deployment Support: When needed, support customer engagements alongside our forward-deployed team: validating AI-generated collateral against real customer specifications and lending DV credibility to deployments.
- Tooling: Set up and evaluate EDA tools, ensuring usability and effective deployment on shared computing resources internally and in customer environments.
WHAT MAKES YOU A GREAT FIT
- 5+ years of experience in digital verification at a major semiconductor or EDA tool company
- Advanced proficiency in SystemVerilog, UVM methodology, and EDA verification tools (vManager, Xcelium, Jasper), with strong Python or Perl scripting
- Proven expertise in end-to-end design verification, including test plan creation, stimulus generation, and feature extraction
- Willingness to occasionally support customer-facing deployment work, including some travel
- Excellent written and spoken communication skills: you can hold the room with a customer's verification lead as credibly as you hold a debug session
BONUS POINTS
- Experience in a customer-facing, field-application, or forward-deployed engineering role at a semiconductor or EDA company
- Hands-on use of LLMs or agentic tools in verification workflows
- Exposure to analog, mixed-signal, or unconventional compute verification
Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.
Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.
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