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NORMAL COMPUTING | BUILD WITH US Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, San Francisco, London, Copenhagen, and Pangyo. THE ROLE As a Hardware Engineer, Architect, you will define the silicon and system microarchitecture for our custom unconventional compute platform—driving the architectural trade-offs that unlock a 100–1000x leap in energy efficiency over traditional digital chips for LLM and diffusion model inference. You will lead the hardware/software co-design efforts to break the von Neumann memory wall. By translating transformer architectures (KV-cache management, attention mechanisms) and diffusion execution flows into custom mixed-signal compute tiles, memory hierarchies, and tile interconnects, you will set the blueprint for our hardware. Working closely with compiler, RTL, and analog teams, you will build performance models, establish microarchitectural specifications, and ensure our custom silicon delivers maximum throughput-per-watt on real-world generative AI workloads. WHAT YOU WILL OWN - Compute Architecture: Help define the architecture and microarchitecture of novel AI accelerator compute blocks: PE array design, datapath organization, and support for efficiency techniques such as sparsity exploitation and reduced-precision computation. The compute tile is the surface where Normal's research advantages have to show up in silicon, and you are one of the people responsible for making sure they do. - Workload-to-Hardware Translation: Translate workload analysis and research findings into hardware specifications. Identify where architectural innovation creates the most leverage, define the structures that realize it, and produce microarchitecture documents unambiguous enough for RTL engineers to implement against. You work closely with them through implementation, not over the wall from it. - Full-Stack PPA Tradeoffs: Reason across the full stack and defend PPA tradeoffs at every level. Move between algorithm-level workload behavior, memory hierarchy, on-chip interconnect, and physical design constraints. Make the call when the data is incomplete, and articulate why under scrutiny from our Systems Architect and the research team. - ISA Co-Design: Partner with the compiler lead on ISA co-design. The programming model and the microarchitecture are defined together, and you are accountable for both sides meeting in the middle. - Prototyping Strategy: Direct block-level pre-silicon validation. Decide which microarchitecture questions need to be answered, and the appropriate platform. Partner with our FPGA Design Engineers, who own implementation and bring-up, to de-risk decisions before tapeout. Work with the Systems Architect to make sure there are no gaps from block to System-level validation. - Research Fluency: Stay current with the AI accelerator research landscape and be able to articulate clearly where Normal's approach differs from existing solutions and why that matters. This is a research-adjacent seat and you are expected to read, possibly publish, and not just consume. WHAT MAKES YOU A GREAT FIT - A degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent work experience. PhD welcome but not required; the bar is the work, not the credential. - Substantial experience in architecture or microarchitecture of high-performance digital systems: AI accelerators, compute engines, or similarly complex logic. You have shaped and directed the structures inside a chip, not just consumed them from the outside. - Fluency moving between algorithm-level analysis and hardware specification. You can read a profile of a workload and translate it into datapath widths, pipeline stages, and area/power estimates without losing the thread on either side. - Experience with simulation-driven architecture. You have used cycle-accurate or analytical models to make and defend design decisions before RTL exists, and you know which questions each tool can answer and which it cannot. - Familiarity with quantization and reduced-precision approaches for inference and their implementation implications. You understand the cost of a bit at the hardware level, not just the model level. - Experience writing microarchitecture specifications and working closely with RTL engineers through implementation. - Proficiency in Python or C++ for performance modeling and analysis, and familiarity with SystemVerilog or equivalent RTL. - Comfort operating in an environment where the architecture is actively being discovered alongside the work. You do not need the answer to be already known to make progress on it. Equal Employment Opportunity Statement Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status. Accessibility Accommodations Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com. Privacy Notice By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.

Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.

Engineering

85 days ago

Hardware Engineer, Physical Design

Normal Computing · Palo Alto, California, United States

Pay

$200k–400k

Setting

Hybrid

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NORMAL COMPUTING | BUILD WITH US Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul. THE ROLE As a Physical Design Engineer at Normal, you will own the end-to-end silicon realization path, taking complex architectures from synthesis and physical floorplanning all the way through timing signoff and GDSII tapeout. Sitting at the intersection of custom ASIC design and our hardware-algorithm co-designed systems, you will shape physical feasibility early in the design cycle by working shoulder-to-shoulder with RTL and architecture teams. You'll drive the full backend implementation flow—optimizing floorplanning, place-and-route (P&R), clock tree synthesis (CTS), static timing analysis (STA), and physical verification (DRC/LVS) to achieve aggressive power, performance, and area (PPA) targets. We are looking for a seasoned engineer who thrives in cross-functional environments and takes pride in tapeout-proven execution. The ideal candidate brings a meticulous approach to physical signoff, maintains clarity in fast-paced build cycles, and is excited to solve the physical constraints of novel computing architectures. WHAT YOU WILL OWN - Physical Implementation & Flow: Lead the full netlist-to-GDSII physical design flow, including floorplanning, power grid design, placement, clock tree synthesis (CTS), and place-and-route (P&R). - Timing Closure & STA: Own static timing analysis (STA), timing constraints creation/validation, and signoff timing closure across all operating corners and modes. - Power, Area, and Signal Integrity: Drive physical optimization for power, performance, and area (PPA), as well as power integrity (IR/EM) and crosstalk analysis. - Physical Signoff & Verification: Execute full chip/block physical signoff checks, including DRC, LVS, ERC, and antenna fixes, ensuring seamless handoff to the foundry. - Design & Floorplan Reviews: Collaborate closely with RTL, architecture, and DFT teams to influence early floorplanning, macro placement, pin assignments, and physical feasibility. - Tapeout & Post-Silicon Support: Create and execute tapeout checklists, manage final stream-out processes, and support post-silicon physical debugging and bring-up as needed. WHAT MAKES YOU A GREAT FIT - Tapeout Track Record: At least 3+ successful tapeouts from netlist to signoff, ideally across advanced technology nodes. - PD Flow Expertise: Deep hands-on experience with industry-standard physical design tools (e.g., Innovus, IC Compiler II, Tempus, PrimeTime, Pegasus, Calibre) across floorplanning, P&R, CTS, and signoff timing closure. - Backend Debugging Instincts: Strong problem-solving skills in analyzing and resolving STA timing bottlenecks, IR/EM drop issues, crosstalk, and complex DRC/LVS signoff violations. - Cross-Functional Feasibility: Ability to collaborate effectively with RTL, architecture, and DFT teams to influence floorplanning, pin placement, and early physical feasibility. BONUS POINTS - Experience at an AI or high-performance compute (HPC) chip startup where design, verification, and PD work in tight iteration cycles. - Experience with custom memory/macro floorplanning, hierarchical top-level implementation, or advanced packaging (e.g., chiplets, 2.5D/3D integration). - Hands-on experience developing or maintaining automated TCL/Python scripting frameworks for physical design flows. Equal Employment Opportunity Statement Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status. Accessibility Accommodations Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com. Privacy Notice By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Applicant Privacy Notice https://normalcomputing.com/applicant-privacy-notice.

Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.

Engineering

97 days ago

Hardware Engineer, PCB

Normal Computing · New York City, New York, USA

Pay

$200k–400k

Setting

Hybrid

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Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.

Engineering

113 days ago

Silicon Software Lead

Normal Computing · New York City, New York, USA

Pay

$200k–400k

Setting

Hybrid

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NORMAL COMPUTING | BUILD WITH US Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, San Francisco, London, Copenhagen, and Pangyo. THE ROLE Normal's ASIC computes using stochastic analog dynamics in memory, and the software layer that makes it programmable and performant for real inference workloads does not yet exist in any standard form. As our Silicon Software Lead, you will lead the team that creates it: the compiler, runtime, kernels, drivers, and hardware abstraction layer that turn our chip into a platform. You will set technical direction, stay hands-on in the stack, and co-design with hardware architects so that software constraints shape the silicon rather than arriving after it. This is a role for someone who has built software for hardware that did not exist yet, and wants to do it where the software genuinely impacts and optimizes the hardware. WHAT YOU WILL OWN - Team Leadership: Lead and grow the silicon software team spanning compiler, runtime, and systems software, staying close enough to the code to review designs and unblock hard problems directly. - Software Stack Architecture: Own the architecture of the stack from ML framework ingestion through compilation, scheduling, and memory management to execution on Normal hardware. - Software/Hardware Co-Design: Partner with silicon architects on ISA definition and the hardware abstraction layer, ensuring the chip is compilable and programmable, not just simulatable. - Runtime and Tooling: Drive development of the runtime, kernels, drivers, profiling, and debugging tools that make the hardware usable for real inference workloads. - Simulation-to-Silicon Continuity: Keep the software stack running against simulation, FPGA prototypes, and silicon as the hardware matures, so software development never waits on tapeout. - Roadmap and Hiring: Set the silicon software roadmap, define milestones against the hardware program, and hire the engineers who deliver it. WHAT MAKES YOU A GREAT FIT - Substantial experience building software stacks for accelerators or non-standard hardware targets: compilers, runtimes, kernels, or drivers - Experience leading engineers as a technical lead or manager while staying hands-on in design and code - Strong systems programming skills in C++, Rust, or equivalent, with fluency in Python - Deep understanding of ML inference workloads and the constraints that shape their execution on hardware - Experience with compiler frameworks such as MLIR or LLVM, or with inference runtimes and kernel development - Comfort building software for hardware that is still evolving, from simulation through bring-up - Track record of hiring and developing strong systems engineers BONUS POINTS - Experience taking an accelerator software stack from zero to production at a startup or new hardware program - Experience with in-memory compute, processing-in-memory, or analog hardware interfaces - Contributions to open-source compiler or runtime infrastructure - Experience with hardware-software co-design where software insights shaped ISA or architecture decisions Equal Employment Opportunity Statement Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status. Accessibility Accommodations Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com. Privacy Notice By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.

Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.

Engineering

113 days ago

Hardware Engineer, RTL

Normal Computing · Palo Alto, California, United States

Pay

$200k–400k

Setting

Hybrid

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NORMAL COMPUTING | BUILD WITH US Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul. THE ROLE As an RTL Design Engineer at Normal, you will design and verify the digital logic at the heart of Normal's thermodynamic hardware. This work sits at the intersection of classical ASIC design, novel computing architectures, and a development environment where the hardware and the algorithms are built together, not in sequence. You will own RTL from microarchitecture to tapeout: writing microarchitecture specifications, creating synthesizable SystemVerilog, working with design verification engineers fully test the design using conventional and formal methods, and working closely with physical design to make sure the design meets area and timing constraints. Because Normal's chips are not standard accelerators, the RTL engineer here is closer to first-principles decisions than at a larger company. You will be shaping architecture, not just implementing it. This is a role for an engineer who collaborates effectively across teams, including architecture, verification and physical design. The strongest candidates have taped out silicon, written RTL and helped close coverage, and are comfortable working in an environment where the specification is still being developed in parallel. WHAT YOU WILL OWN - RTL Design: Write and own synthesizable RTL in SystemVerilog across blocks ranging from datapath logic to control and memory interfaces. - Microarchitecture: Work with architecture to translate high-level specifications into implementable microarchitectures. - Verification: Work closely with the verification team to review verification plans, assist on debug, and become a partner in closing coverage. - Physical Design Collaboration: Collaborate with physical design on timing closure, floorplanning constraints, and DFT. - Design Reviews: Participate in design reviews and contribute to architecture decisions, not just implementation. - Tapeout & Bring-up: Support tapeout preparation, integration, and post-silicon bring-up as needed. WHAT MAKES YOU A GREAT FIT - Hands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place-and-route - Experience in closing coverage to a high level - At least one tapeout in your background, from any node and any company size - Experience working on datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront - Strong debugging instincts across simulation, waveforms, and formal counterexamples - Ability to work directly with architects and physical designers without needing a large intermediary layer - Industry experience in ASIC or SoC design BONUS POINTS - Experience at an AI chip company where design and verification were tightly coupled - Open-source RTL contributions to projects like Chipyard, OpenTitan, or CVA6 - Familiarity with RISC-V or other open ISAs - Experience with AI-assisted RTL or EDA tooling in your design workflow - Exposure to physical design constraints, floorplanning, or timing-driven RTL development Equal Employment Opportunity Statement Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status. Accessibility Accommodations Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com. Privacy Notice By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.

Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.

Engineering

113 days ago

Hardware Engineer, FPGA

Normal Computing · New York City, New York, USA

Pay

$250k–340k

Setting

Hybrid

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NORMAL COMPUTING | BUILD WITH US Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul. THE ROLE Validating conventional silicon is a solved discipline. Validating silicon that computes with noise is not, and you will be the one who figures out how. As our FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early software development, and building the test infrastructure for post-silicon bring-up and characterization. Your scope spans the entire FPGA lifecycle: selecting hardware platforms, implementing complex RTL, debugging in the lab, and writing the software that drives it all, working daily with our silicon, EDA, and research teams. WHAT YOU WILL OWN - FPGA Platform Ownership: Lead the selection, procurement, and bring-up of FPGA prototyping platforms (e.g., HAPS, VCU118/VPK180-class boards, or custom hardware) for pre-silicon RTL validation and software development. - RTL Implementation: Adapt and implement complex ASIC RTL onto FPGA targets, including multi-clock-domain architectures, CDC bridges, and timing closure on dense designs. - IP Integration: Integrate in-house designs with third-party and vendor IP; serve as the expert on the AMD/Xilinx ecosystem (Vivado IP Integrator, transceivers, memory controllers). - High-Speed Interfaces: Design, implement, and validate high-speed I/O with a focus on PCIe: our accelerators ship as PCIe cards in standard servers. - Post-Silicon Validation: Build FPGA-based "tester" designs for silicon bring-up, device characterization, and automated test environments. - Hardware-Software Stack: Develop the software layer around the hardware: Python/C++ hardware abstraction, register-map generation, and automated build and regression flows. - Lab Debug: Root-cause complex timing and functional issues in real time using ILA/Vivado Analyzer, oscilloscopes, logic analyzers, and BER/eye-diagram characterization of high-speed links. WHAT MAKES YOU A GREAT FIT - Proven industry experience taking FPGA designs from RTL through timing closure to validated hardware, ideally in an ASIC prototyping, emulation, or high-growth hardware environment. - Expert-level SystemVerilog and/or VHDL for synthesis, with deep proficiency in Xilinx Vivado (synthesis, place & route, timing closure, IP catalog). - Hands-on experience implementing and debugging PCIe, plus AXI/AHB, SPI, UART, JTAG, and other common interfaces. - Strong Python for automation, test, and build tooling. - Strong board-level bring-up and lab debugging skills on real hardware. - Startup mindset: you work independently, pivot quickly, and run at ambiguous problems that span hardware, software, and physics. BONUS POINTS - Verification frameworks like Cocotb or UVM - Experience deploying ML models to FPGAs (hls4ml, FINN, or custom NN-to-RTL flows), or building real-time, sub-microsecond signal processing pipelines. - Mixed-signal ASIC exposure: digital front-ends, ADC/DAC interfaces, or analog compute. - SERDES tuning and signal integrity fundamentals. - CI/CD for hardware (GitLab CI, Docker-based build and test). Equal Employment Opportunity Statement Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status. Accessibility Accommodations Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com. Privacy Notice By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.

Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.

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