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Hardware Engineer, Architect
Normal Computing · Palo Alto, California, United States
Pay
$105k–250k
Setting
Hybrid
NORMAL COMPUTING | BUILD WITH US
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, San Francisco, London, Copenhagen, and Pangyo.
THE ROLE
As a Hardware Engineer, Architect, you will define the silicon and system microarchitecture for our custom unconventional compute platform—driving the architectural trade-offs that unlock a 100–1000x leap in energy efficiency over traditional digital chips for LLM and diffusion model inference.
You will lead the hardware/software co-design efforts to break the von Neumann memory wall. By translating transformer architectures (KV-cache management, attention mechanisms) and diffusion execution flows into custom mixed-signal compute tiles, memory hierarchies, and tile interconnects, you will set the blueprint for our hardware. Working closely with compiler, RTL, and analog teams, you will build performance models, establish microarchitectural specifications, and ensure our custom silicon delivers maximum throughput-per-watt on real-world generative AI workloads.
WHAT YOU WILL OWN
- Compute Architecture: Help define the architecture and microarchitecture of novel AI accelerator compute blocks: PE array design, datapath organization, and support for efficiency techniques such as sparsity exploitation and reduced-precision computation. The compute tile is the surface where Normal's research advantages have to show up in silicon, and you are one of the people responsible for making sure they do.
- Workload-to-Hardware Translation: Translate workload analysis and research findings into hardware specifications. Identify where architectural innovation creates the most leverage, define the structures that realize it, and produce microarchitecture documents unambiguous enough for RTL engineers to implement against. You work closely with them through implementation, not over the wall from it.
- Full-Stack PPA Tradeoffs: Reason across the full stack and defend PPA tradeoffs at every level. Move between algorithm-level workload behavior, memory hierarchy, on-chip interconnect, and physical design constraints. Make the call when the data is incomplete, and articulate why under scrutiny from our Systems Architect and the research team.
- ISA Co-Design: Partner with the compiler lead on ISA co-design. The programming model and the microarchitecture are defined together, and you are accountable for both sides meeting in the middle.
- Prototyping Strategy: Direct block-level pre-silicon validation. Decide which microarchitecture questions need to be answered, and the appropriate platform. Partner with our FPGA Design Engineers, who own implementation and bring-up, to de-risk decisions before tapeout. Work with the Systems Architect to make sure there are no gaps from block to System-level validation.
- Research Fluency: Stay current with the AI accelerator research landscape and be able to articulate clearly where Normal's approach differs from existing solutions and why that matters. This is a research-adjacent seat and you are expected to read, possibly publish, and not just consume.
WHAT MAKES YOU A GREAT FIT
- A degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent work experience. PhD welcome but not required; the bar is the work, not the credential.
- Substantial experience in architecture or microarchitecture of high-performance digital systems: AI accelerators, compute engines, or similarly complex logic. You have shaped and directed the structures inside a chip, not just consumed them from the outside.
- Fluency moving between algorithm-level analysis and hardware specification. You can read a profile of a workload and translate it into datapath widths, pipeline stages, and area/power estimates without losing the thread on either side.
- Experience with simulation-driven architecture. You have used cycle-accurate or analytical models to make and defend design decisions before RTL exists, and you know which questions each tool can answer and which it cannot.
- Familiarity with quantization and reduced-precision approaches for inference and their implementation implications. You understand the cost of a bit at the hardware level, not just the model level.
- Experience writing microarchitecture specifications and working closely with RTL engineers through implementation.
- Proficiency in Python or C++ for performance modeling and analysis, and familiarity with SystemVerilog or equivalent RTL.
- Comfort operating in an environment where the architecture is actively being discovered alongside the work. You do not need the answer to be already known to make progress on it.
Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.
Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.
Software Engineer, Agent Systems
Normal Computing · New York City, New York, USA
Pay
$200k–400k
Setting
Hybrid
NORMAL COMPUTING | BUILD WITH US
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.
THE ROLE
As a Software Engineer at Normal, you will build the backend runtimes and distributed systems behind our AI products. You'll design orchestration services, execution environments, internal APIs, persistence layers, and observability systems that allow AI agents to perform long-running work reliably.
These systems coordinate workloads across distributed environments, execute code and tools securely, preserve state across long-running sessions, and recover cleanly from failures. Your work will turn ambitious AI prototypes into dependable products used in real customer workflows.
The role spans backend, AI, and platform engineering. Its focus is the application and runtime layer but not general-purpose cloud infrastructure or company-wide developer operations. You'll work closely with product, AI, research, and platform engineers to define the interfaces between AI capabilities, execution environments, and production services.
On any given day, you might design the execution model for a new AI capability, build an orchestration service for autonomous workflows, improve the scheduling and isolation of distributed workloads, or create an API that makes a complex runtime capability easy for other engineers to use.
WHAT YOU WILL OWN
- Runtime and Orchestration: Build the services that manage agent execution, session lifecycles, long-running workflows, and distributed workloads.
- Backend Systems and APIs: Design reliable services, data models, and internal APIs used by product engineers, AI engineers, and execution systems.
- State and Failure Handling: Develop clear models for persistence, retries, queues, leases, cancellation, recovery, and other distributed-systems concerns.
- Execution Environments: Build software that schedules and manages containerized workloads in Kubernetes-backed environments, including lifecycle, isolation, autoscaling, and resource management.
- Reliability and Observability: Make evolving systems easier to operate through thoughtful metrics, tracing, debugging tools, and well-defined failure modes.
- Developer Experience: Create abstractions and tools that allow other engineers to extend the platform without needing to understand every underlying implementation detail.
- Prototype-to-Production Engineering: Turn promising prototypes into durable systems by clarifying boundaries, hardening critical paths, and introducing operational patterns that scale.
- Technical Design: Facilitate design discussions around runtime architecture, API boundaries, state management, execution models, and operational tradeoffs.
WHAT MAKES YOU A GREAT FIT
- 4+ years of software engineering experience in backend systems, distributed systems, developer platforms, production infrastructure, or a related area.
- Strong backend engineering fundamentals, including API design, data modeling, concurrency, debugging, and testing.
- Experience designing and operating production services where reliability, observability, and maintainability matter.
- Experience reasoning about distributed state and failure modes, including retries, queues, leases, scheduling, idempotency, and long-running workflows.
- Practical experience with containers and Kubernetes-backed systems, including workload lifecycle, networking, resource limits, and production debugging.
- Experience with production data systems such as Postgres, Redis or Valkey, and object storage.
- Experience building orchestration systems, workflow engines, job schedulers, sandboxes, developer platforms, or distributed execution systems.
- A track record of designing APIs and abstractions that other engineers can use confidently.
- Pragmatic judgment in fast-moving environments: you know when to improve an abstraction, simplify it, or ship the straightforward version.
- A strong sense of ownership for how your software behaves in production and how effectively others can use it.
BONUS POINTS
- Experience building systems for AI agents, model orchestration, code execution, or other LLM-powered products.
- Deep Kubernetes knowledge, such as controllers, scheduling, networking, storage, autoscaling, or resource isolation.
- Experience with secure or sandboxed code execution.
- Background in reliability engineering, infrastructure software, or developer platforms at meaningful scale.
- Experience working in high-growth environments where systems and ownership boundaries are still taking shape.
Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.
Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.
Hardware Engineer, PCB
Normal Computing · New York City, New York, USA
Pay
$200k–400k
Setting
Hybrid
NORMAL COMPUTING | BUILD WITH US
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.
THE ROLE
Normal Computing is redefining computing for the next 20 years by optimizing LLM and Diffusion inference by 100–1000x through combining thermodynamic computing and CIM technology. You will own the end-to-end development of our CIM substrate from architecture and schematic design to layout, tapeout, custom PCB development, and post-silicon bring-up.
WHAT YOU WILL OWN
- End-to-end PCB design flow: lead the full PCB development cycle including research, design, and evaluation of custom chips
- Silicon bring-up: lead post-silicon correlation and validation efforts including root-cause analysis and general debug
- PCB bring-up: ensure the PCB you designed and manufactured is fully functional as intended
- Cross-functional collaboration: work alongside analog, digital, and ML engineers to further improve system-level PPA.
WHAT MAKES YOU A GREAT FIT
- Owned multiple PCBs end-to-end through design, simulation, fabrication and bringup
- Familiar with common PCB tools, including Altium, Allegro, OrCAD, Xpedition
- Built PCBs for expansion formats like PCIe, and including components like FPGAs, high-speed memories, flash memories, and various connectors like 100G ethernet
BONUS POINTS
- Lead, fabricated, brought up custom PCBs to evaluate custom CIM chips
- Experienced and comfortable in a lab bench environment including soldering with a microscope
- Have used scripting languages (i.e. Python, Perl) to automate design flows and data post-processing
Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.
Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.
Silicon Software Lead
Normal Computing · New York City, New York, USA
Pay
$200k–400k
Setting
Hybrid
NORMAL COMPUTING | BUILD WITH US
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, San Francisco, London, Copenhagen, and Pangyo.
THE ROLE
Normal's ASIC computes using stochastic analog dynamics in memory, and the software layer that makes it programmable and performant for real inference workloads does not yet exist in any standard form. As our Silicon Software Lead, you will lead the team that creates it: the compiler, runtime, kernels, drivers, and hardware abstraction layer that turn our chip into a platform. You will set technical direction, stay hands-on in the stack, and co-design with hardware architects so that software constraints shape the silicon rather than arriving after it.
This is a role for someone who has built software for hardware that did not exist yet, and wants to do it where the software genuinely impacts and optimizes the hardware.
WHAT YOU WILL OWN
- Team Leadership: Lead and grow the silicon software team spanning compiler, runtime, and systems software, staying close enough to the code to review designs and unblock hard problems directly.
- Software Stack Architecture: Own the architecture of the stack from ML framework ingestion through compilation, scheduling, and memory management to execution on Normal hardware.
- Software/Hardware Co-Design: Partner with silicon architects on ISA definition and the hardware abstraction layer, ensuring the chip is compilable and programmable, not just simulatable.
- Runtime and Tooling: Drive development of the runtime, kernels, drivers, profiling, and debugging tools that make the hardware usable for real inference workloads.
- Simulation-to-Silicon Continuity: Keep the software stack running against simulation, FPGA prototypes, and silicon as the hardware matures, so software development never waits on tapeout.
- Roadmap and Hiring: Set the silicon software roadmap, define milestones against the hardware program, and hire the engineers who deliver it.
WHAT MAKES YOU A GREAT FIT
- Substantial experience building software stacks for accelerators or non-standard hardware targets: compilers, runtimes, kernels, or drivers
- Experience leading engineers as a technical lead or manager while staying hands-on in design and code
- Strong systems programming skills in C++, Rust, or equivalent, with fluency in Python
- Deep understanding of ML inference workloads and the constraints that shape their execution on hardware
- Experience with compiler frameworks such as MLIR or LLVM, or with inference runtimes and kernel development
- Comfort building software for hardware that is still evolving, from simulation through bring-up
- Track record of hiring and developing strong systems engineers
BONUS POINTS
- Experience taking an accelerator software stack from zero to production at a startup or new hardware program
- Experience with in-memory compute, processing-in-memory, or analog hardware interfaces
- Contributions to open-source compiler or runtime infrastructure
- Experience with hardware-software co-design where software insights shaped ISA or architecture decisions
Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.
Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.
Hardware Engineer, RTL
Normal Computing · New York City, New York, USA
Pay
$200k–400k
Setting
Hybrid
NORMAL COMPUTING | BUILD WITH US
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.
THE ROLE
As an RTL Design Engineer at Normal, you will design and verify the digital logic at the heart of Normal's thermodynamic hardware. This work sits at the intersection of classical ASIC design, novel computing architectures, and a development environment where the hardware and the algorithms are built together, not in sequence.
You will own RTL from microarchitecture to tapeout: writing microarchitecture specifications, creating synthesizable SystemVerilog, working with design verification engineers fully test the design using conventional and formal methods, and working closely with physical design to make sure the design meets area and timing constraints. Because Normal's chips are not standard accelerators, the RTL engineer here is closer to first-principles decisions than at a larger company. You will be shaping architecture, not just implementing it.
This is a role for an engineer who collaborates effectively across teams, including architecture, verification and physical design. The strongest candidates have taped out silicon, written RTL and helped close coverage, and are comfortable working in an environment where the specification is still being developed in parallel.
WHAT YOU WILL OWN
- RTL Design: Write and own synthesizable RTL in SystemVerilog across blocks ranging from datapath logic to control and memory interfaces.
- Microarchitecture: Work with architecture to translate high-level specifications into implementable microarchitectures.
- Verification: Work closely with the verification team to review verification plans, assist on debug, and become a partner in closing coverage.
- Physical Design Collaboration: Collaborate with physical design on timing closure, floorplanning constraints, and DFT.
- Design Reviews: Participate in design reviews and contribute to architecture decisions, not just implementation.
- Tapeout & Bring-up: Support tapeout preparation, integration, and post-silicon bring-up as needed.
WHAT MAKES YOU A GREAT FIT
- Hands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place-and-route
- Experience in closing coverage to a high level
- At least one tapeout in your background, from any node and any company size
- Experience working on datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront
- Strong debugging instincts across simulation, waveforms, and formal counterexamples
- Ability to work directly with architects and physical designers without needing a large intermediary layer
- Industry experience in ASIC or SoC design
BONUS POINTS
- Experience at an AI chip company where design and verification were tightly coupled
- Open-source RTL contributions to projects like Chipyard, OpenTitan, or CVA6
- Familiarity with RISC-V or other open ISAs
- Experience with AI-assisted RTL or EDA tooling in your design workflow
- Exposure to physical design constraints, floorplanning, or timing-driven RTL development
Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.
Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.
Hardware Engineer, FPGA
Normal Computing · New York City, New York, USA
Pay
$200k–400k
Setting
Hybrid
NORMAL COMPUTING | BUILD WITH US
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.
THE ROLE
Validating conventional silicon is a solved discipline. Validating silicon that computes with noise is not, and you will be the one who figures out how. As our FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early software development, and building the test infrastructure for post-silicon bring-up and characterization. Your scope spans the entire FPGA lifecycle: selecting hardware platforms, implementing complex RTL, debugging in the lab, and writing the software that drives it all, working daily with our silicon, EDA, and research teams.
WHAT YOU WILL OWN
- FPGA Platform Ownership: Lead the selection, procurement, and bring-up of FPGA prototyping platforms (e.g., HAPS, VCU118/VPK180-class boards, or custom hardware) for pre-silicon RTL validation and software development.
- RTL Implementation: Adapt and implement complex ASIC RTL onto FPGA targets, including multi-clock-domain architectures, CDC bridges, and timing closure on dense designs.
- IP Integration: Integrate in-house designs with third-party and vendor IP; serve as the expert on the AMD/Xilinx ecosystem (Vivado IP Integrator, transceivers, memory controllers).
- High-Speed Interfaces: Design, implement, and validate high-speed I/O with a focus on PCIe: our accelerators ship as PCIe cards in standard servers.
- Post-Silicon Validation: Build FPGA-based "tester" designs for silicon bring-up, device characterization, and automated test environments.
- Hardware-Software Stack: Develop the software layer around the hardware: Python/C++ hardware abstraction, register-map generation, and automated build and regression flows.
- Lab Debug: Root-cause complex timing and functional issues in real time using ILA/Vivado Analyzer, oscilloscopes, logic analyzers, and BER/eye-diagram characterization of high-speed links.
WHAT MAKES YOU A GREAT FIT
- Proven industry experience taking FPGA designs from RTL through timing closure to validated hardware, ideally in an ASIC prototyping, emulation, or high-growth hardware environment.
- Expert-level SystemVerilog and/or VHDL for synthesis, with deep proficiency in Xilinx Vivado (synthesis, place & route, timing closure, IP catalog).
- Hands-on experience implementing and debugging PCIe, plus AXI/AHB, SPI, UART, JTAG, and other common interfaces.
- Strong Python for automation, test, and build tooling.
- Strong board-level bring-up and lab debugging skills on real hardware.
- Startup mindset: you work independently, pivot quickly, and run at ambiguous problems that span hardware, software, and physics.
BONUS POINTS
- Verification frameworks like Cocotb or UVM
- Experience deploying ML models to FPGAs (hls4ml, FINN, or custom NN-to-RTL flows), or building real-time, sub-microsecond signal processing pipelines.
- Mixed-signal ASIC exposure: digital front-ends, ADC/DAC interfaces, or analog compute.
- SERDES tuning and signal integrity fundamentals.
- CI/CD for hardware (GitLab CI, Docker-based build and test).
Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.
Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.
Software Engineer, Backend
Normal Computing · New York City, New York, USA
Pay
$200k–400k
Setting
Hybrid
Infrastructure Software Engineer
Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.
Forward Deployed Engineer
Normal Computing · New York City, New York, USA
Pay
$200k–400k
Setting
Hybrid
NORMAL COMPUTING | BUILD WITH US
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, San Francisco, London, Copenhagen, and Pangyo.
THE ROLE
The cost of taping out silicon is enormous, and the complexity of verification makes multiple tapeouts hard to avoid. Normal EDA accelerates this work as an AI platform for collaborative silicon engineering: a single source of truth across the chip lifecycle, learning continuously from the teams that use it. As a Forward Deployed Engineer, you own our EDA system inside a customer's environment. Embedded directly with our partners, you adapt our platform to their data, workflows, and design challenges, working alongside our account executive and a deployment strategist to make the deployment a success.
You thrive as a problem-solver and take pride in winning over customers along with the rest of your team. You will be debugging distributed systems, building new product features, post-training models, and working in various silicon-native languages such as SystemVerilog. Note that many different kinds of candidates could be well-qualified for this role, even with non-overlapping expertise (e.g. ML background vs. silicon background).
WHAT YOU WILL OWN
- Production Problem-Solving: Diagnose issues in our system, the model, the data, or the workflow. Work deep in both Normal's systems and the customer's environment to resolve them, and close the loop with their engineers.
- Evaluation Against Reality: Design and run evals against real customer workflows, validating generated artifacts against their specifications so model behavior holds up in production.
- Platform Integration: Integrate the platform with each customer's data, design flows, and tooling, working with their production codebases and against their existing infrastructure.
- Customer Signal: Embedded with silicon design teams, translate their constraints into model and platform requirements, and carry that signal back to Normal's research, product, and platform teams to shape what gets built next.
- Continual Learning: Post-train Normal's models on-prem on proprietary customer data and trajectories to customize to their workflow, tooling, and style preferences. Build the continual-learning loops that turn their engineers' feedback into system knowledge, so model quality compounds across the engagement.
- Judgment Ahead of Playbook: Make the calls on what to build, what to skip, and when to push back on a request that would compromise what ships. Codify what works into patterns that raise the floor for every engagement after yours.
WHAT MAKES YOU A GREAT FIT
- Great at problem-solving and tracking down issues wherever they are in the stack
- Strong software engineering fundamentals: proficient in Python, comfortable in production codebases, distributed-systems literate
- Hands-on experience with the modern ML stack: prompt engineering, fine-tuning, evals, agentic patterns, model deployment
- Willingness and ability to go deep on semiconductor verification workflows. You will spend significant time inside UVM testbenches, SystemVerilog codebases, and design specifications. Prior experience is a strong advantage, but what matters is whether you can build fluency fast and earn credibility with verification engineers
- An ability to ship ML systems inside customer or production environments where model behavior had to hold up against real-world data
- Calm in ambiguity: you make good decisions with incomplete information, and you know when to act and when to ask
- Comfortable with travel when needed; anywhere between a few days for customer meetings and a few months for longer-term customer projects
BONUS POINTS
- Direct experience with EDA, semiconductor design flows, verification workflows (UVM, SystemVerilog, coverage-driven verification), or other areas of silicon engineering
- Built or led an FDE or customer-deployment function from the ground up at an earlier-stage company
- Open-source contributions or publications in AI or ML venues
Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.
Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.
AI Engineer
Normal Computing · New York City, New York, USA
Pay
$200k–400k
Setting
Hybrid
Staff AI Engineer
Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.
Design Verification Engineer
Normal Computing · New York City, New York, USA
Pay
$110k–205k
Setting
Hybrid
NORMAL COMPUTING | BUILD WITH US
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, San Francisco, London, Copenhagen, and Pangyo.
THE ROLE
As a Design Verification Engineer at Normal, you will verify our own physics-inspired ASICs on the road to tapeout, and set the quality bar for what our AI learns: reviewing generated verification collateral and shaping the standards our models train against. From time to time, you may also be tapped to support a customer deployment alongside our forward-deployed team, where your verification credibility helps our AI platform land inside real DV flows. The through-line is your DV expertise, applied to silicon that computes differently than anything you've verified before, and to the AI that is changing how verification gets done. This is a seat for a verification engineer who wants their craft to compound rather than repeat.
WHAT YOU WILL OWN
- Thermodynamic ASIC Verification: Own design verification for Normal's internal silicon: testbench environments, assertions, and coverage from design documents through functional coverage and closure, supporting the program to tapeout.
- AI Product Refinement: Review AI-generated verification collateral to shape product strategy and tool usability in collaboration with the ML and product teams.
- Data Quality Bar: Set the quality standard for verification training data: define rubrics, curate golden examples, and partner with our Data team, who own the pipelines, so our models learn from verification artifacts a real DV engineer would sign off on.
- Deployment Support: When needed, support customer engagements alongside our forward-deployed team: validating AI-generated collateral against real customer specifications and lending DV credibility to deployments.
- Tooling: Set up and evaluate EDA tools, ensuring usability and effective deployment on shared computing resources internally and in customer environments.
WHAT MAKES YOU A GREAT FIT
- 5+ years of experience in digital verification at a major semiconductor or EDA tool company
- Advanced proficiency in SystemVerilog, UVM methodology, and EDA verification tools (vManager, Xcelium, Jasper), with strong Python or Perl scripting
- Proven expertise in end-to-end design verification, including test plan creation, stimulus generation, and feature extraction
- Willingness to occasionally support customer-facing deployment work, including some travel
- Excellent written and spoken communication skills: you can hold the room with a customer's verification lead as credibly as you hold a debug session
BONUS POINTS
- Experience in a customer-facing, field-application, or forward-deployed engineering role at a semiconductor or EDA company
- Hands-on use of LLMs or agentic tools in verification workflows
- Exposure to analog, mixed-signal, or unconventional compute verification
Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.
Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.
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