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Senior Hardware Recruiter
Normal Computing · Palo Alto, California, United States
$165k–195k
6 days ago
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Analog Design Engineer (custom DRAM circuits)
Normal Computing · Palo Alto, California, United States
$200k–400k
8 days ago
♡
Physical Design Manager
Normal Computing · Palo Alto, California, United States
$200k–400k
8 days ago
♡
System Architect Lead
Normal Computing · Palo Alto, California, United States
$200k–400k
44 days ago
♡
Talent Operations Specialist
Normal Computing · Palo Alto, California, United States
$140k–175k
61 days ago
♡
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Senior Hardware Recruiter
Normal Computing · Palo Alto, California, United States
Pay
$165k–195k
Setting
Hybrid
NORMAL COMPUTING | BUILD WITH US
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.
The Role
Recruiting silicon talent is a specialist's craft: the candidate pool is small, every strong architect and DV engineer is fielding multiple offers, and the people you're hunting can smell a recruiter who doesn't know what a tapeout is.
As a Technical Hardware Recruiter, you will work on full-cycle recruiting for Normal's silicon organization. You will partner directly with hiring managers who are themselves deep technologists, source candidates who aren't looking, and close people who have every option.
What You'll Own
- Full-Cycle Recruiting: Manage an end-to-end recruitment process for senior hardware, ASIC, and silicon architecture roles from intake through close, flexing to AI, silicon software, and other technical searches as priorities shift.
- Strategic Sourcing: Identify and engage top-tier talent in unconventional silicon architecture, design verification, and systems architecture: people who are rarely on the market and need a reason to talk.
- Engineering Partnership: Act as a strategic partner to engineering hiring managers, aligning on candidate qualifications, technical bars, and calibration as searches evolve.
- Process Discipline: Run the WHO Method for talent calibration and maintain high-efficiency interview loops, targeting 4-5 rounds maximum so great candidates don't die in process.
- ATS Ownership: Maintain impeccable data hygiene and pipeline flow in Ashby: clean stages, honest statuses, reporting the team can trust.
- Brand Ambassadorship: Represent Normal Computing at industry events like DAC, engaging specialized candidates in the rooms where they actually gather.
What Makes You a Great Fit
- 6+ years of full-cycle technical recruiting, including direct experience recruiting AI, ASIC, silicon, or semiconductor engineers: RTL, DV, physical design, architecture, or adjacent roles
- A track record of closing senior engineers against competing offers: you know how to sell equity, risk, and conviction, not just a comp number
- Technical literacy across the deep-tech landscape: AI silicon, and custom ASIC development — you can hold a credible intake conversation with a chip architect
- Advanced fluency in Ashby (or comparable ATS) for candidate tracking, reporting, and process automation
- Operational excellence: low ego, comfortable with ambiguity, and able to move real work forward at the volume of a scaling startup
Bonus Points
- Exposure to AI/ML and software engineering recruiting in addition to hardware expertise
- Experience recruiting for unconventional computing or physics-based hardware architectures
- Previous experience in a high-growth venture-backed startup, semiconductor company, or research lab
Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Applicant Privacy Notice https://normalcomputing.com/applicant-privacy-notice.
Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.
Analog Design Engineer (custom DRAM circuits)
Normal Computing · Palo Alto, California, United States
Pay
$200k–400k
Setting
Hybrid
NORMAL COMPUTING | BUILD WITH US
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.
THE ROLE
As an Analog Hardware Engineer, you will build the core mixed-signal technology powering our unconventional computing architecture.
You will design unique analog circuits, creating library cells as well as macros, to support a unique computational architecture. Working alongside silicon architecture, digital, and layout teams, you will own the end-to-end analog development from clean-sheet circuit design through parasitic extraction and silicon bring-up to unlock unprecedented throughput-per-watt.
WHAT YOU WILL OWN
- Analog design flow methodology: lead the full analog development cycle including research, exploratory design
- Develop or acquire analog IP for use in Normal Silicon
- Acquire or help direct analog EDA tool development
- Evaluation of memory designs, including SRAM, DRAM, and CIM architectures
WHAT MAKES YOU A GREAT FIT
- Developed analog IP from spec to GDSII in modern technologies, taped out and brought up.
- Worked on memory technologies (i.e. SRAM, DRAM) on core level (bitcell arrays and peripheral circuits)
- Designed and characterized custom bitcells in schematic and layout
- Fluent in the Cadence flow: Virtuoso, Spectre, Assembler, Extraction, Layout, HSMC, Characterization
- Deep understanding of noise and variation and their impacts on silicon performance and reliability
BONUS POINTS
- Lead, taped out, brought up CIM chips
- Experienced and comfortable in a chip measurement environment for debug and characterization
- Have used AI and/or scripting languages (i.e. Python, Perl) to automate design flows and data post-processing
Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Applicant Privacy Notice https://normalcomputing.com/applicant-privacy-notice.
Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.
Physical Design Manager
Normal Computing · Palo Alto, California, United States
Pay
$200k–400k
Setting
Hybrid
NORMAL COMPUTING | BUILD WITH US
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.
THE ROLE
As a Physical Design Manager at Normal, leading the team owns the end-to-end silicon realization path, taking complex architectures from synthesis and physical floorplanning all the way through timing signoff and GDSII tapeout. Sitting at the intersection of custom ASIC design and our hardware-algorithm co-designed systems, you will shape physical feasibility early in the design cycle by working shoulder-to-shoulder with RTL and architecture teams. You'll drive the full backend implementation flow—optimizing floorplanning, place-and-route (P&R), clock tree synthesis (CTS), static timing analysis (STA), and physical verification (DRC/LVS) to achieve aggressive power, performance, and area (PPA) targets.
We are looking for a seasoned engineer and manager who thrives in cross-functional environments and takes pride in tapeout-proven execution. The ideal candidate brings effective team building and leaders, and a meticulous approach to physical signoff, maintains clarity in fast-paced build cycles, and is excited to solve the physical constraints of novel computing architectures.
WHAT YOU WILL OWN
- Physical Design Team Hiring & Leadership: Provide leadership of the PD team, including necessary hiring to support the plan, and individual guidance and performance feedback
- Project Planning: Create work estimates and schedule to support an aggressive tapeout plan
- EDA tools acquisition: Specify and help negotiate the appropriate EDA tools to support the physical design methodology
- Design & Floorplan Reviews: Collaborate closely with RTL, architecture, and DFT teams to influence early floorplanning, macro placement, pin assignments, and physical feasibility.
- Physical Implementation & Flow: Lead the full netlist-to-GDSII physical design flow, including floorplanning, power grid design, placement, clock tree synthesis (CTS), and place-and-route (P&R).
- Timing Closure & STA: Own static timing analysis (STA), timing constraints creation/validation, and signoff timing closure across all operating corners and modes.
- Power, Area, and Signal Integrity: Drive physical optimization for power, performance, and area (PPA), as well as power integrity (IR/EM) and crosstalk analysis.
- Physical Signoff & Verification: Execute full chip/block physical signoff checks, including DRC, LVS, ERC, and antenna fixes, ensuring seamless handoff to the foundry.
- Tapeout & Post-Silicon Support: Create and execute tapeout checklists, manage final stream-out processes, and support post-silicon physical debugging and bring-up as needed.
WHAT MAKES YOU A GREAT FIT
- Tapeout Track Record: Lead at least 3+ successful tapeouts from netlist to signoff, ideally across advanced technology nodes.
- PD Flow Expertise: Deep hands-on experience with industry-standard physical design tools (e.g., Innovus, IC Compiler II, Tempus, PrimeTime, Pegasus, Calibre) across floorplanning, P&R, CTS, and signoff timing closure.
- Backend Debugging Instincts: Strong problem-solving skills in analyzing and resolving STA timing bottlenecks, IR/EM drop issues, crosstalk, and complex DRC/LVS signoff violations.
- Cross-Functional Feasibility: Ability to collaborate effectively with RTL, architecture, and DFT teams to influence floorplanning, pin placement, and early physical feasibility.
- Managerial experience: at least 7 years experience in role
BONUS POINTS
- Experience at an AI or high-performance compute (HPC) chip startup where design, verification, and PD work in tight iteration cycles.
- Experience with custom memory/macro floorplanning, hierarchical top-level implementation, or advanced packaging (e.g., chiplets, 2.5D/3D integration).
- Hands-on experience developing or maintaining automated TCL/Python scripting frameworks for physical design flows.
Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Applicant Privacy Notice https://normalcomputing.com/applicant-privacy-notice.
Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.
Product Manager
Normal Computing · New York City, New York, USA
Pay
$206k–225k
Setting
Hybrid
NORMAL COMPUTING | BUILD WITH US
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.
THE ROLE
As an early-career Product Manager, you'll work with the Product Lead and the engineering teams to help build the AI systems and autoresearch platform our ASIC team needs to tapeout unconventional, physics-based architecture. We are rethinking the chip design system from the ground up, automating the process of research: exploring the full design space, generating candidate architectures, evaluating them at appropriate levels of fidelity, and feeding learnings from experiments run in hardware labs and deployed silicon into the next generation chip. Domains of exploration include RTL optimization, design verification, and continual learning from experiment results. You'll help decide what we build, then be accountable for delivering on the incremental milestones to tapeout.
On any given day, you might sit with a chip architect benchmarking novel architectures, shadow a verification debug session and come back with a proposal for what to automate, scope out the requirements and success criteria for a custom EDA tool, or prototype an experiment dashboard. This is a building role. You'll write specs, run experiments, and use coding agents to prototype and land fixes yourself. When you have an idea, we would rather you spend an afternoon prototyping a rough version than a week describing it.
No semiconductor background is required to start. In your first few months the bar is understanding how the team works, asking the questions that move a design discussion forward, and earning trust by following through on deliverables.
WHAT YOU'LL OWN
- AI tooling scope: Investigate where the ASIC team's time actually goes, decide what we build, then be accountable for whether it gets used.
- Specs and prototypes: Write the requirements docs and user journeys that engineering builds from. Where a working prototype communicates faster than a document, build the prototype instead.
- Prototype to production: Work with engineers to turn a promising prototype into something the ASIC team can rely on.
- Shipping small changes: Work in the codebase with coding agents, open PRs for bug fixes or UI changes, learn from code reviews from engineers, and develop judgment about which changes are yours to make.
WHAT MAKES YOU A GREAT FIT
- A degree in CS, EE, physics, math, or similar, or the equivalent taught to yourself.
- 1-3 years of experience in product management, engineering, research, technical program management, or a related technical role.
- You can point to something that was your idea and that you made real.
- Fluency with coding agents. You already use Claude Code, Codex, Cursor, or something similar as a normal part of how you work.
- Experience building or evaluating LLM-powered products.
- Clarity of communication in both speaking and writing.
- Comfort with ambiguity. Much of what you work on will be underspecified. You should be able to take a vague problem, frame it, and come back with a proposal.
- Interest in how chips are designed.
BONUS POINTS
- Coursework, research, or internship experience in chip architectures, digital design, verification, or hardware performance modeling.
- Exposure to SystemVerilog.
- Familiarity with the mechanisms underlying LLM inference
Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Applicant Privacy Notice https://normalcomputing.com/applicant-privacy-notice.
Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.
Platform Engineer
Normal Computing · Palo Alto, California, United States
Pay
$200k–400k
Setting
Hybrid
We’re hiring a Platform Engineer to own and evolve the critical infrastructure that powers Normal’s engineering organization. While our infrastructure is distributed across multiple locations, this position involves managing the local physical infrastructure (network, servers) and requires regular on-site presence in Mountain View and occasional travels to the New York office.
Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.
System Architect Lead
Normal Computing · Palo Alto, California, United States
Pay
$200k–400k
Setting
Hybrid
NORMAL COMPUTING | BUILD WITH US
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.
The Role
As a Hardware System Design Architect, you will lead the system architecture design of Normal’s AI compute hardware end-to-end, from initial concept to specification, design reviews, integration, and deployment. You will guide system-level decisions spanning boards, chassis, interconnects, and rack-scale system design, collaborating closely across hardware, software, and other engineering teams to ensure system designs meet performance and workload requirements.
You’ll define system requirements and specifications, evaluate architectural options, and drive key technical decisions as our hardware platforms evolve. You’ll evaluate partner and vendor designs against our requirements, identify technical gaps and schedule risks early, and lead system-level tradeoffs. You’ll play a central role in bringing these pieces together into cohesive, high-performance AI compute systems and driving the overall system from architecture through deployment.
What You Will Own
- Lead hardware system architecture from initial concept and requirements through design reviews, integration, and production deployment.
- Translate workload and performance requirements into hardware decisions, working closely with cross-functional teams and external partners.
- Lead architecture design across boards, chassis, and racks, including system topology, power, thermal, scale-up and scale-out fabrics, and networking.
- Define and own bring-up, system integration, validation and qualification strategy.
What Makes You a Great Fit
- Significant experience architecting complex compute hardware systems, spanning server or machine-level designs through rack-scale platforms
- Experience taking hardware systems from early requirements and architecture through specification, integration, bring-up, validation, and production deployment
- Experience working with ODMs, suppliers, and other hardware partners, including reviewing designs, defining technical requirements, and driving technical issues to resolution
- Degree in Electrical Engineering, Computer Engineering, or a related field
Bonus Points
- Experience designing high-performance AI compute systems at server and rack scale
- Experience bringing novel hardware architectures into production-scale compute systems
- Advanced degree in Electrical Engineering, Computer Engineering, or a related field
Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.
Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.
Talent Operations Specialist
Normal Computing · Palo Alto, California, United States
Pay
$140k–175k
Setting
Hybrid
NORMAL COMPUTING | BUILD WITH US
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.
THE ROLE
As our Talent Operations Specialist, you will own and scale the engine behind how Normal hires world-class talent across hardware, software, and AI. You sit at the strategic center of our global talent organization, acting as the right hand to our Head of Talent to build high-efficiency recruiting workflows, maintain our data integrity, and eliminate friction across five global time zones.
At Normal, we operate in a fast-moving, highly evolving environment where priorities shift and ambiguity is constant. You are someone who thrives on context-switching—effortlessly pivoting between long-term system architecture and immediate operational priorities. Rather than just manually moving candidates through calendars, you take complete ownership of our talent infrastructure: optimizing Ashby, building real-time executive dashboards, automating scheduling flows, and ensuring our recruiting operation runs on rails as we scale.
WHAT YOU’LL OWN
- Recruiting Systems & Ashby ATS Architecture: Serve as the primary admin for Ashby. Permission and seat management, pipeline stages, build custom candidate communication templates, configure auto-scheduling rules, and manage integrations across our tech stack (Slack, Notion, AI Notetaker, Google Workspace).
- Candidate Data Integrity and Compliance Operations: Own the day-to-day health of candidate data in Ashby. Maintain retention and consent configurations, execute scheduled record dispositions, monitor duplicate and fraud-flagged records, and keep candidate data practices aligned with Normal’s published privacy commitments across US and global applicants.
- Talent Analytics & Reporting: Build and maintain recruiting dashboards to track funnel conversion, candidate velocity, source effectiveness, and interviewer loads. Deliver data-backed insights to the Head of Talent and leadership to optimize hiring SLAs.
- Process Automation & AI Workflow Optimization: Evaluate, scope, and govern AI tools, automated scheduling logic, and low-code integrations to reduce admin overhead, improve response times, and elevate candidate experience.
- Interviewer & Hiring Manager Enablement: Partner with recruiting leads to standardize interview loops, establish scorecard guidelines, onboard new interviewers, and build clear Notion documentation for team-wide hiring practices.
- Global Logistics & Vendor Operations: Oversee candidate touchpoints and job board posting distribution across US, European, and APAC markets.
- Special Projects & Strategic Support: Partner directly with the Head of Talent on high-impact initiatives, including headcount planning support, talent brand launches, recruiting event logistics, and strategic ad-hoc projects.
- Interview Coordination (Backup and Surge): Provide secondary coverage for interview scheduling when volume spikes or primary coordination is unavailable. Roughly 15-20% of the role.
WHAT MAKES YOU A GREAT FIT
- Talent Ops or Advanced Coordination: You have experience in a fast-scaling tech startup, high-growth environment, or deep-tech company.
- Extreme Ownership & Accountability: You treat the recruiting engine as your own product. You flag problems while they are small, fix broken processes without being asked, and close loops relentlessly.
- Comfort with Context-Switching & Ambiguity: Highly adaptable and composed when priorities shift in a fast-paced, evolving startup environment.
- Mastery of ATS Infrastructure: Hands-on experience administering Ashby (or Greenhouse/Lever) with a track record of setting up structured pipelines, custom fields, offer workflows, and automated scheduling rules.
- Data-Fluent & Analytical: Comfortable working with recruiting metrics, building custom reports, identifying pipeline bottlenecks, and presenting data clearly to stakeholders.
- Systems & Automation Mindset: Passionate about documentation, process hygiene, and using modern tools (Slack, Notion, AI assistants, low-code automations) to replace manual administrative work.
- Global & Cross-Functional Comfort: Experienced in navigating multi-time-zone communication (US, Europe, APAC) with high attention to detail and proactive communication default.
BONUS POINTS
- Advanced experience specifically with Ashby
- Experience supporting fast-moving technology startups.
- Background in setting up interviewer calibration modules or candidate NPS loops
Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.
Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.
ASIC Architect
Normal Computing · Palo Alto, California, United States
Pay
$200k–400k
Setting
Hybrid
NORMAL COMPUTING | BUILD WITH US
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, San Francisco, London, Copenhagen, and Pangyo.
THE ROLE
As a Hardware Engineer, Architect, you will define the silicon and system microarchitecture for our custom unconventional compute platform—driving the architectural trade-offs that unlock a 100–1000x leap in energy efficiency over traditional digital chips for LLM and diffusion model inference.
You will lead the hardware/software co-design efforts to break the von Neumann memory wall. By translating transformer architectures (KV-cache management, attention mechanisms) and diffusion execution flows into custom mixed-signal compute tiles, memory hierarchies, and tile interconnects, you will set the blueprint for our hardware. Working closely with compiler, RTL, and analog teams, you will build performance models, establish microarchitectural specifications, and ensure our custom silicon delivers maximum throughput-per-watt on real-world generative AI workloads.
WHAT YOU WILL OWN
- Compute Architecture: Help define the architecture and microarchitecture of novel AI accelerator compute blocks: PE array design, datapath organization, and support for efficiency techniques such as sparsity exploitation and reduced-precision computation. The compute tile is the surface where Normal's research advantages have to show up in silicon, and you are one of the people responsible for making sure they do.
- Workload-to-Hardware Translation: Translate workload analysis and research findings into hardware specifications. Identify where architectural innovation creates the most leverage, define the structures that realize it, and produce microarchitecture documents unambiguous enough for RTL engineers to implement against. You work closely with them through implementation, not over the wall from it.
- Full-Stack PPA Tradeoffs: Reason across the full stack and defend PPA tradeoffs at every level. Move between algorithm-level workload behavior, memory hierarchy, on-chip interconnect, and physical design constraints. Make the call when the data is incomplete, and articulate why under scrutiny from our Systems Architect and the research team.
- ISA Co-Design: Partner with the compiler lead on ISA co-design. The programming model and the microarchitecture are defined together, and you are accountable for both sides meeting in the middle.
- Prototyping Strategy: Direct block-level pre-silicon validation. Decide which microarchitecture questions need to be answered, and the appropriate platform. Partner with our FPGA Design Engineers, who own implementation and bring-up, to de-risk decisions before tapeout. Work with the Systems Architect to make sure there are no gaps from block to System-level validation.
- Research Fluency: Stay current with the AI accelerator research landscape and be able to articulate clearly where Normal's approach differs from existing solutions and why that matters. This is a research-adjacent seat and you are expected to read, possibly publish, and not just consume.
WHAT MAKES YOU A GREAT FIT
- A degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent work experience. PhD welcome but not required; the bar is the work, not the credential.
- Substantial experience in architecture or microarchitecture of high-performance digital systems: AI accelerators, compute engines, or similarly complex logic. You have shaped and directed the structures inside a chip, not just consumed them from the outside.
- Fluency moving between algorithm-level analysis and hardware specification. You can read a profile of a workload and translate it into datapath widths, pipeline stages, and area/power estimates without losing the thread on either side.
- Experience with simulation-driven architecture. You have used cycle-accurate or analytical models to make and defend design decisions before RTL exists, and you know which questions each tool can answer and which it cannot.
- Familiarity with quantization and reduced-precision approaches for inference and their implementation implications. You understand the cost of a bit at the hardware level, not just the model level.
- Experience writing microarchitecture specifications and working closely with RTL engineers through implementation.
- Proficiency in Python or C++ for performance modeling and analysis, and familiarity with SystemVerilog or equivalent RTL.
- Comfort operating in an environment where the architecture is actively being discovered alongside the work. You do not need the answer to be already known to make progress on it.
Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.
Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.
Hardware Engineer, Physical Design
Normal Computing · Palo Alto, California, United States
Pay
$200k–400k
Setting
Hybrid
NORMAL COMPUTING | BUILD WITH US
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.
THE ROLE
As a Physical Design Engineer at Normal, you will own the end-to-end silicon realization path, taking complex architectures from synthesis and physical floorplanning all the way through timing signoff and GDSII tapeout. Sitting at the intersection of custom ASIC design and our hardware-algorithm co-designed systems, you will shape physical feasibility early in the design cycle by working shoulder-to-shoulder with RTL and architecture teams. You'll drive the full backend implementation flow—optimizing floorplanning, place-and-route (P&R), clock tree synthesis (CTS), static timing analysis (STA), and physical verification (DRC/LVS) to achieve aggressive power, performance, and area (PPA) targets.
We are looking for a seasoned engineer who thrives in cross-functional environments and takes pride in tapeout-proven execution. The ideal candidate brings a meticulous approach to physical signoff, maintains clarity in fast-paced build cycles, and is excited to solve the physical constraints of novel computing architectures.
WHAT YOU WILL OWN
- Physical Implementation & Flow: Lead the full netlist-to-GDSII physical design flow, including floorplanning, power grid design, placement, clock tree synthesis (CTS), and place-and-route (P&R).
- Timing Closure & STA: Own static timing analysis (STA), timing constraints creation/validation, and signoff timing closure across all operating corners and modes.
- Power, Area, and Signal Integrity: Drive physical optimization for power, performance, and area (PPA), as well as power integrity (IR/EM) and crosstalk analysis.
- Physical Signoff & Verification: Execute full chip/block physical signoff checks, including DRC, LVS, ERC, and antenna fixes, ensuring seamless handoff to the foundry.
- Design & Floorplan Reviews: Collaborate closely with RTL, architecture, and DFT teams to influence early floorplanning, macro placement, pin assignments, and physical feasibility.
- Tapeout & Post-Silicon Support: Create and execute tapeout checklists, manage final stream-out processes, and support post-silicon physical debugging and bring-up as needed.
WHAT MAKES YOU A GREAT FIT
- Tapeout Track Record: At least 3+ successful tapeouts from netlist to signoff, ideally across advanced technology nodes.
- PD Flow Expertise: Deep hands-on experience with industry-standard physical design tools (e.g., Innovus, IC Compiler II, Tempus, PrimeTime, Pegasus, Calibre) across floorplanning, P&R, CTS, and signoff timing closure.
- Backend Debugging Instincts: Strong problem-solving skills in analyzing and resolving STA timing bottlenecks, IR/EM drop issues, crosstalk, and complex DRC/LVS signoff violations.
- Cross-Functional Feasibility: Ability to collaborate effectively with RTL, architecture, and DFT teams to influence floorplanning, pin placement, and early physical feasibility.
BONUS POINTS
- Experience at an AI or high-performance compute (HPC) chip startup where design, verification, and PD work in tight iteration cycles.
- Experience with custom memory/macro floorplanning, hierarchical top-level implementation, or advanced packaging (e.g., chiplets, 2.5D/3D integration).
- Hands-on experience developing or maintaining automated TCL/Python scripting frameworks for physical design flows.
Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Applicant Privacy Notice https://normalcomputing.com/applicant-privacy-notice.
Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.
Hardware Engineer, PCB
Normal Computing · New York City, New York, USA
Pay
$200k–400k
Setting
Hybrid
NORMAL COMPUTING | BUILD WITH US
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.
THE ROLE
Normal Computing is redefining computing for the next 20 years by optimizing LLM and Diffusion inference by 100–1000x through combining thermodynamic computing and CIM technology. You will own the end-to-end development of our CIM substrate from architecture and schematic design to layout, tapeout, custom PCB development, and post-silicon bring-up.
WHAT YOU WILL OWN
- End-to-end PCB design flow: lead the full PCB development cycle including research, design, and evaluation of custom chips
- Silicon bring-up: lead post-silicon correlation and validation efforts including root-cause analysis and general debug
- PCB bring-up: ensure the PCB you designed and manufactured is fully functional as intended
- Cross-functional collaboration: work alongside analog, digital, and ML engineers to further improve system-level PPA.
WHAT MAKES YOU A GREAT FIT
- Owned multiple PCBs end-to-end through design, simulation, fabrication and bringup
- Familiar with common PCB tools, including Altium, Allegro, OrCAD, Xpedition
- Built PCBs for expansion formats like PCIe, and including components like FPGAs, high-speed memories, flash memories, and various connectors like 100G ethernet
BONUS POINTS
- Lead, fabricated, brought up custom PCBs to evaluate custom CIM chips
- Experienced and comfortable in a lab bench environment including soldering with a microscope
- Have used scripting languages (i.e. Python, Perl) to automate design flows and data post-processing
Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.
Listed by Normal Computing for a position based in the United States. Employers on this board attest they are hiring domestically.
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