As a Design Verification Engineer at Lightmatter, you will find yourself at the heart of a dynamic, interdisciplinary team. Your role will involve close collaboration with our digital design experts, using UVM testbench techniques to rigorously verify their designs. Your responsibilities will include working alongside photonic and analog designers, gaining a deep understanding of their innovative designs, and applying Real Number Modeling (RNM) and AMS verification methods. This critical function ensures the integrity of their work. We are hiring at multiple levels. 

Your interaction with the Architecture team will be crucial in comprehending system requirements and spearheading performance verification. This role offers a unique platform to enhance your skills across a spectrum of areas including UVM, AMS modeling, mixed-signal verification, post-silicon validation formal verification, emulation, and both performance modeling and verification.

Responsibilities

• Define and enhance the DV methodologies required for integrated digital, analog, and photonic devices with a strong emphasis on emulation for design verification.
• Create and execute test plans to ensure high-quality tapeouts that meet functional and performance goals, while leveraging emulation where appropriate.
• Collaborate with architects, DV engineers, digital designers, and analog/photonics designers to define validation flows.
• Create reusable and scalable test bench components that enable efficient and effective verification.
• Close coverage and finish all DV signoff requirements, with a focus on leveraging mixed signal simulations to achieve high coverage metrics
• Work on block level and full chip design verification.
• Integrate analog design IPs from vendors and internal teams and develop verification environments for simulation and emulation.
• Work with analog design engineers to create behavioral models for analog designs and with digital design engineers to integrate models/testcase/checkers into upper levels

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, a related field, or equivalent experience
• Minimum of 8 years of design verification and SystemVerilog experience
• 2+ years of experience in Python
• Expertise in developing with the UVM library
• Experience with simulators such as Xcelium, ModelSim, Questa, or VCS
• Strong problem solver and collaborator

Preferred Qualifications 

• Master’s degree or higher in Electrical Engineering, Computer Engineering, a related field, or equivalent experience with 6 years of relevant experience 
• Experience with post-silicon validation and debug
• Experience with AMS verification

About this role

We are hiring a Physical Design Timing Engineer to help drive backend digital execution for some of the leading photonics based interconnect solutions. You will work alongside a team of world-class scientists and engineers in defining how the system will be optimized and trailblaze problems that are new to the industry. If your passion is innovation, solving challenging technical problems and doing impactful work you should join our team.

In this job you will be responsible for timing constraints development, STA and timing closure on  leading edge CMOS technologies and flows. This includes synthesis through place and route, timing closure, and tapeout signoff.

Responsibilities

• Drive the STA sign-off  for our flagship Silicon photonics chips at various technology nodes. 
• Analyze fab guidelines and work with the methodology team to incorporate sign off corners, margins, and derates into timing analysis flows and methodologies.
• Collaborate with the  architecture, RTL, and DFT teams to analyze the timing complexities and develop consolidated timing modes and constraints for synthesis, along with PnR and chip timing sign-off flows.
• Analyze and understand the tradeoffs between power/performance and area goals to drive them into overall chip implementation flows.
• Run full-chip STA and accurately project the timing summary across scenarios.
• Leverage Tempus/PrimeTime to automate timing ECO generation for effective closure and support physical design implementation.
• Document best practices and lessons learned to drive continuous improvements in future projects.

Qualifications:

• Bachelor’s degree in Electrical Engineering or Computer engineering
• 12 years of Physical Design experience, with a minimum of 5 years hands-on experience in ASIC STA and timing constraints development, timing closure with Cadence or Synopsys tools 
• Experience in driving timing closure by effectively managing on-chip variation derates, optimizing multi-mode multi-corner constraints, and implementing robust clock tree building strategies
• Well versed with scripting languages like TCL and Python, PERL, or Shell
• Strong problem solving skills with attention to every technical aspect
• Be a strong team player with clear and precise communication skills

Preferred Qualifications:

• Master’s degree in Electrical Engineering or Computer engineering
• A minimum of 8 years of hands-on experience in ASIC STA and timing constraints development, timing closure with Cadence or Synopsys tools