About this Role

We are hiring a Staff Photonics Design and Layout Engineer to join our rapidly growing team. In this role, you will be working closely with photonics, product, architecture, analog, digital and packaging teams to floorplan, design and layout block- and chip-scale photonic circuits. You will be tasked with supporting photonic products throughout their entire development cycle, from a clean sheet concept all the way to the tapeout and bring-up. Leveraging our industry-leading and proprietary photonics integration and verification flow and tools, you will be working on verifying that all blocks and circuits meet their performance design targets.

Join a tight-knit team where each individual’s contributions directly influence the success of the company and product. You'll have the opportunity to build innovative integrated photonic solutions from the ground up and tackle groundbreaking challenges. Work with people who love to build and who thrive in diverse technical environments where great ideas are prioritized.

Responsibilities

• Understand product requirements and work with customer-facing teams to help identify optimal photonics solutions
• Work on clean sheet design and layout of block- and system-level photonic circuits 
• Work with analog, digital and packaging teams to ensure seamless integration of on-chip photonics with other subsystems
• Perform rigorous layout-driven photonic simulation and verification. Identify performance bottlenecks and troubleshoot issues.
• Help develop and improve photonic layout, verification and integration flows for multiple photonic processes and foundries
• Contribute to proprietary PDK development
• Engage in problem solving and contribute to new photonic chip designs and architectures.
• Publish novel results, and participate in premier optics/photonics conferences.

Qualifications

• MS + 10 years or PhD + 3 years of industry experience in Electrical Engineering, Physics, Photonics, or related discipline
• Excellent understanding of fundamental concepts of silicon photonics
• Familiarity with of a wide variety of silicon photonics devices, knowledge of their performance metrics and design trade-offs
• Proficiency with Python
• Experience with script-based photonic circuit design and layout using GDSFactory or similar
• Demonstrated track record of multiple photonic tapeouts
• Excellent communication skills, with demonstrated ability to collaborate effectively with multidisciplinary teams
• Demonstrated ability to independently work on both highly constrained and loosely defined problems

Preferred Qualifications

• Experience with product-grade photonic tapeouts
• Experience with foundry and custom PDKs
• Experience with photonic and/or analog circuit design in Cadence Virtuoso
• Strong project execution skills, with the ability to handle multiple priorities and meet project milestones.

About the job

We are hiring a Senior Technical Program Manager to help coordinate the engineering effort behind Lightmatter’s AI and Chiplet Interconnect products. You will lead program management for Lightmatter’s silicon hardware engineering team from design through production, collaborating with engineering teams across the company to plan and drive the team's objectives. This role will span silicon development, packaging, assembly, and test phases.

In this role, you will collaborate constantly with engineering teams across the company to plan and drive objectives for the group. You will gather requirements, drive quality initiatives, manage technical risks, and plan for all phases of the silicon design process. In addition, you’ll partner with executives and engineering leadership to develop and manage milestones and schedules for the many moving parts that need to come together.

Responsibilities

• Organize and expertly drive planning, scheduling, and day-to-day execution to support Lightmatter’s silicon, package and systems development
• Collaborate with leads and engineering teams in effectively estimating and prioritizing tasks in order to maintain excellent quality on a realistic delivery schedule
• Develop and lead project plans (scope, schedule, and budget) to ensure alignment with key partners and business needs
• Manage project schedules and quality, identify possible issues and risks, and clearly communicate them to project stakeholders
• Facilitate recurring project meetings and operational checkpoint activities throughout the life cycle of projects
• Set clear and targeted communication to management of project information, including project plan, key dates, and project status
• Provide the required hands-on project management, cross-functional coordination, and internal and external team communications to deliver outstanding program outcomes
• Take responsibility for release schedules and milestones in a fast-paced environment
• Opportunities to engage with vendors and customers in external program

Qualifications

• 8+ years of experience with silicon design and tapeout, and product qualification
• Bachelor’s degree in a technical field
• Experience with product qualification lifecycle (EVT, DVT, PVT)
• Prior semiconductor engineering experience (chip, systems, or product)
• Experience influencing decisions and leading teams in a matrix environment
• Attention to detail and strong ability to multitask in an ever-changing fast-paced environment
• Proven ability to identify and implement process improvements, characterized by a high level of responsiveness and passion for enhancing operational efficiency
• Expert user of program management tools such as MS-Project, Asana, Smartsheet, or similar
• Excellent communications and technical presentation skills

Preferred Qualifications

• Knowledge of photonic structures, optical communication, and laser solutions
• Experience setting up project management initiatives from scratch in either a startup or a new business unit environment

Job Details: Job Description: At the heart of Intel's groundbreaking product advancements, the Logic Technology Development (LTD) organization is a powerhouse of process technology innovation. Our relentless pursuit of excellence and innovation propels Intel's Foundry strategy, ensuring that we not only meet but exceed the aspirations of our global customers. As we continue to lead the semiconductor industry, we are enhancing our technological capabilities to guarantee the triumph of our customers' diverse and ambitious projects. Your Role in Intel's Foundry Revolution: As a Foundry Technology Development - Staff Yield Engineer, you will be at the forefront of Intel's collaborative journey with our foundry partners. Your expertise will be pivotal in guiding our customers through the intricate journey of product development, starting from testing and validation to New Product Introduction (NPI) phase to the High Volume Manufacturing (HVM). You will play a vital role in overseeing the wafer manufacturing process and ensuring a seamless transition into volume production. This is a unique opportunity to be part of a team that is not just participating in the industry but actively shaping its future. We are seeking a broad range of semiconductor expertise across the range of foundry technology development. Based on experience, potential areas may include: Serve as the yield point of contact through the cycle of foundry product development, from design to initial High Volume Manufacturing (HVM) Define yield goal and roadmap for foundry customer silicon by collaborating with Intel Foundry Services (IFS), Technology Development (TD), and Product Integration Collaborate with TD Process Integration, Device, Defect Metro, and Lab to identify yield detractors and yield enhancement opportunities, specifically for foundry customer silicon Provide yield / defect density projection for different types of customer silicon, including test chips, shuttles, and products Track inline process and non-process changes to incorporate the changepoints into yield prediction model Develop yield models to identify potential parametric and defective loss components and support Process Integration, Device and Module teams to develop projects to eliminate systematic yield losses Support yield analysis of logic, SRAM, and other types of devices on foundry customer silicon Establish correlations between critical inline metrics and yield for better inline control and end of line projection Engage side-by-side with Product Integration and Device teams in customer silicon execution, such as skew split planning and DOE Lead investigations and root-causing on yield signals for foundry customer silicon Identify opportunities to optimize foundry product development operational systems and methodologies to improve efficiency and standardization Work as the technical interface between foundry and both internal stakeholders and external customers Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications: Bachelor’s Degree in Electrical Engineering, Materials Science, Physics, Chemical Engineering or other relevant engineering or physical science discipline with 6+ years of relevant work experience OR Master's Degree in Electrical Engineering, Materials Science, Physics, Chemical Engineering or other relevant engineering or physical science with 4+ years of relevant work experience OR PhD Degree in Electrical Engineering, Materials Science, Physics, Chemical Engineering or other relevant engineering or physical science discipline with 2+ years of industry experience The years of relevant work experience listed above must be in the field in at least one of the following areas: Semiconductor yield engineering Analysis of yield post silicon yield signal and root-causing Preferred Qualifications: 3+ years of semiconductor direct yield analysis and engineering experience 3+ direct experience in yield pareto, projection and yield roadmap construction 3+ years of experience within a foundry team, or foundry customer yield collaboration 3+ years of experience interpreting product data including inline, e-test and SORT data, finding failure root cause and inline indicator and driving for solutions Knowledge on inline inspection method, electrical test structures and SORT programs Exposure to fabless design house product development Foundry customer service experience and evidence of strong customer orientation. For information on Intel’s immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship Information Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Texas, Austin Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $155,520.00-255,200.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. Intel’s official careers website. Find your next job and take on projects that shape tomorrow’s technology. Benefits Internships Life at Intel Locations Recruitment Process

We’re looking for a Recruiting Coordinator to be the engine behind Lightmatter’s rapid growth. We are scaling fast, and we need a logistics expert who can navigate the complexities of our interview process with speed and precision. As a key representative of our brand during the scheduling phase, you will ensure that every engineer, technologist, and professional has a positive and organized experience. You will play a vital role in helping Lightmatter assemble the world-class talent needed to build the future of photonic-based computing.

Responsibilities

• Own end-to-end scheduling for a high volume of candidate interviews and debrief meetings across all hiring stages, from phone screens to final rounds.
• Coordinate complex virtual and in-person interview loops spanning multiple time zones while keeping appropriate stakeholders informed while ensuring every participant has confirmed availability, has accurate links, and necessary context ahead of each session.
• Manage real-time calendar conflicts and last-minute reschedules with speed and composure, keeping the hiring process moving without disruption.
• Serve as the logistical point of contact between candidates and internal teams, delivering a seamless, professional experience from first touchpoint to offer.
• Partner with recruiters to continuously audit and improve scheduling workflows, update email templates, identify opportunities to introduce smarter tooling or eliminate manual steps.
• Orchestrate a polished "day-of" experience for every candidate, confirming access, surfacing the right information, and providing live support so no one walks into an interview unprepared.
• Bring a high-ownership mindset to the role, stepping in to support the team when requested and upholding the quality of the hiring mission.

Qualifications

• 2+ years of experience in high-volume interview scheduling, managing 50+ interviews per week in a fast-paced, tech-focused environment.
• Proven ability to coordinate across multiple zones while maintaining scheduling accuracy and a professional candidate experience.
• Track record of managing multiple concurrent hiring pipelines, prioritizing effectively and adapting quickly when schedules shift.
• Tech-savvy with the ability to learn new tools rapidly; comfortable working across ATS platforms (e.g., Greenhouse), scheduling software (e.g., GoodTime, Calendly), and video conferencing tools.
• Strong written and verbal communication skills, direct, polished, and capable of representing the company well in every candidate interaction.
• Service-oriented approach with demonstrated success delivering a high-quality experience to both candidates and internal stakeholders under time pressure.
• Natural process optimizer who actively looks for ways to reduce manual lift and improve scheduling reliability.

Preferred Qualifications

• Bachelor degree.
• Demonstrated ability to work autonomously, exercising sound judgment when recruiters or hiring managers are unavailable.
• Familiarity with Greenhouse or similar ATS and scheduling automation platforms.
• Curiosity about technology and how photonic technology is reshaping AI infrastructure and high-performance networking.

About this role

We are hiring a Physical Design Timing Engineer to help drive backend digital execution for some of the leading photonics based interconnect solutions. You will work alongside a team of world-class scientists and engineers in defining how the system will be optimized and trailblaze problems that are new to the industry. If your passion is innovation, solving challenging technical problems and doing impactful work you should join our team.

In this job you will be responsible for timing constraints development, STA and timing closure on  leading edge CMOS technologies and flows. This includes synthesis through place and route, timing closure, and tapeout signoff.

Responsibilities

• Drive the STA sign-off  for our flagship Silicon photonics chips at various technology nodes. 
• Analyze fab guidelines and work with the methodology team to incorporate sign off corners, margins, and derates into timing analysis flows and methodologies.
• Collaborate with the  architecture, RTL, and DFT teams to analyze the timing complexities and develop consolidated timing modes and constraints for synthesis, along with PnR and chip timing sign-off flows.
• Analyze and understand the tradeoffs between power/performance and area goals to drive them into overall chip implementation flows.
• Run full-chip STA and accurately project the timing summary across scenarios.
• Leverage Tempus/PrimeTime to automate timing ECO generation for effective closure and support physical design implementation.
• Document best practices and lessons learned to drive continuous improvements in future projects.

Qualifications:

• Bachelor’s degree in Electrical Engineering or Computer engineering
• 12 years of Physical Design experience, with a minimum of 5 years hands-on experience in ASIC STA and timing constraints development, timing closure with Cadence or Synopsys tools 
• Experience in driving timing closure by effectively managing on-chip variation derates, optimizing multi-mode multi-corner constraints, and implementing robust clock tree building strategies
• Well versed with scripting languages like TCL and Python, PERL, or Shell
• Strong problem solving skills with attention to every technical aspect
• Be a strong team player with clear and precise communication skills

Preferred Qualifications:

• Master’s degree in Electrical Engineering or Computer engineering
• A minimum of 8 years of hands-on experience in ASIC STA and timing constraints development, timing closure with Cadence or Synopsys tools 

We are hiring a Photonics PDK Modeling Engineer to join our team. In this role, you will lead the development of our internal  Process Design Kit (PDK). You will act as the architect of our component library, bridging the gap between physical device physics and system-level simulation. You will develop robust compact models for active and passive components, ensuring that our simulation environment accurately predicts the behavior of our physical layouts. You will work heavily in Python, applying software engineering rigor to the challenges of photonic hardware design.

Responsibilities

• Develop and maintain a library of pcells using Python-based layout frameworks. Ensure strict synchronization between physical layout, logical netlists, and behavioral models.
• Create and verify behavioral compact models for passive and active devices
• Simulation Infrastructure: Build automated workflows that extract parameters from electromagnetic solvers (FDTD/FEM) and package them into the PDK for circuit-level simulation.
• Model-Hardware Correlation: Validate simulation models against lab measurements. Perform data fitting and statistical analysis to align model parameters with real-world silicon performance.
• Automated Verification: Implement regression testing and Continuous Integration (CI) pipelines to ensure PDK updates do not break legacy designs or connectivity logic.
• Netlist & Connectivity: Own the logic for netlist extraction, ensuring that the connectivity graph generated by the code perfectly matches the physical intent.
  
  

Qualifications

• Master’s +5 years experience or PhD +3 years experience in Electrical Engineering, Photonics, Physics, or related field.
• Deep understanding of photonic device physics and experience in device simulation. 
• Experience building behavioral models for circuit simulators (e.g., Lumerical INTERCONNECT, Cadence, Synopsys OptSim, or custom Python solvers).
• Experienced in Python for modeling, automation, and data analysis. Comfortable with object-oriented programming and scientific libraries (NumPy, SciPy).
• Python based layout experience.

Preferred Qualifications

• Familiarity with GDSFactory, OptoCompiler or KLayout Python scripting.
• Experience with Python-native circuit simulation ecosystems (e.g., SAX, Photontorch, Simphony).
• Experience with Git version control, unit testing (pytest), and CI/CD workflows.
• Prior experience in performing physical layout using foundry-provided process design kits (PDKs), adhering to specific design rules and constraints.
• Experience in taping out and testing large-scale photonic integrated circuits, including familiarity with relevant testing equipment and methodologies.
• Experience doing inverse design
• Possess strong project execution skills, demonstrating the ability to effectively manage multiple design priorities, adhere to project timelines, and meet critical milestones.

We are hiring a Photonics PDK Modeling Engineer to join our team. In this role, you will lead the development of our internal  Process Design Kit (PDK). You will act as the architect of our component library, bridging the gap between physical device physics and system-level simulation. You will develop robust compact models for active and passive components, ensuring that our simulation environment accurately predicts the behavior of our physical layouts. You will work heavily in Python, applying software engineering rigor to the challenges of photonic hardware design.

Responsibilities

• Develop and maintain a library of pcells using Python-based layout frameworks. Ensure strict synchronization between physical layout, logical netlists, and behavioral models.
• Create and verify behavioral compact models for passive and active devices
• Simulation Infrastructure: Build automated workflows that extract parameters from electromagnetic solvers (FDTD/FEM) and package them into the PDK for circuit-level simulation.
• Model-Hardware Correlation: Validate simulation models against lab measurements. Perform data fitting and statistical analysis to align model parameters with real-world silicon performance.
• Automated Verification: Implement regression testing and Continuous Integration (CI) pipelines to ensure PDK updates do not break legacy designs or connectivity logic.
• Netlist & Connectivity: Own the logic for netlist extraction, ensuring that the connectivity graph generated by the code perfectly matches the physical intent.
  
  

Qualifications

• Master’s +5 years experience or PhD +3 years experience in Electrical Engineering, Photonics, Physics, or related field.
• Deep understanding of photonic device physics and experience in device simulation. 
• Experience building behavioral models for circuit simulators (e.g., Lumerical INTERCONNECT, Cadence, Synopsys OptSim, or custom Python solvers).
• Experienced in Python for modeling, automation, and data analysis. Comfortable with object-oriented programming and scientific libraries (NumPy, SciPy).
• Python based layout experience.

Preferred Qualifications

• Familiarity with GDSFactory, OptoCompiler, or KLayout Python scripting.
• Experience with Python-native circuit simulation ecosystems (e.g., SAX, Photontorch, Simphony).
• Experience with Git version control, unit testing (pytest), and CI/CD workflows.
• Prior experience in performing physical layout using foundry-provided process design kits (PDKs), adhering to specific design rules and constraints.
• Experience in taping out and testing large-scale photonic integrated circuits, including familiarity with relevant testing equipment and methodologies.
• Experience doing inverse design
• Possess strong project execution skills, demonstrating the ability to effectively manage multiple design priorities, adhere to project timelines, and meet critical milestones.

We are hiring a Photonics PDK Modeling Engineer to join our team. In this role, you will lead the development of our internal  Process Design Kit (PDK). You will act as the architect of our component library, bridging the gap between physical device physics and system-level simulation. You will develop robust compact models for active and passive components, ensuring that our simulation environment accurately predicts the behavior of our physical layouts. You will work heavily in Python, applying software engineering rigor to the challenges of photonic hardware design.

Responsibilities

• Develop and maintain a library of pcells using Python-based layout frameworks. Ensure strict synchronization between physical layout, logical netlists, and behavioral models.
• Create and verify behavioral compact models for passive and active devices
• Simulation Infrastructure: Build automated workflows that extract parameters from electromagnetic solvers (FDTD/FEM) and package them into the PDK for circuit-level simulation.
• Model-Hardware Correlation: Validate simulation models against lab measurements. Perform data fitting and statistical analysis to align model parameters with real-world silicon performance.
• Automated Verification: Implement regression testing and Continuous Integration (CI) pipelines to ensure PDK updates do not break legacy designs or connectivity logic.
• Netlist & Connectivity: Own the logic for netlist extraction, ensuring that the connectivity graph generated by the code perfectly matches the physical intent.
  
  

Qualifications

• Master’s +5 years experience or PhD +3 years experience in Electrical Engineering, Photonics, Physics, or related field.
• Deep understanding of photonic device physics and experience in device simulation. 
• Experience building behavioral models for circuit simulators (e.g., Lumerical INTERCONNECT, Cadence, Synopsys OptSim, or custom Python solvers).
• Experienced in Python for modeling, automation, and data analysis. Comfortable with object-oriented programming and scientific libraries (NumPy, SciPy).
• Python based layout experience.

Preferred Qualifications

• Familiarity with GDSFactory, OptoCompiler or KLayout Python scripting.
• Experience with Python-native circuit simulation ecosystems (e.g., SAX, Photontorch, Simphony).
• Experience with Git version control, unit testing (pytest), and CI/CD workflows.
• Prior experience in performing physical layout using foundry-provided process design kits (PDKs), adhering to specific design rules and constraints.
• Experience in taping out and testing large-scale photonic integrated circuits, including familiarity with relevant testing equipment and methodologies.
• Experience doing inverse design
• Possess strong project execution skills, demonstrating the ability to effectively manage multiple design priorities, adhere to project timelines, and meet critical milestones.

About this role

We are hiring a Physical Design Timing Engineer to help drive backend digital execution for some of the leading photonics based interconnect solutions. You will work alongside a team of world-class scientists and engineers in defining how the system will be optimized and trailblaze problems that are new to the industry. If your passion is innovation, solving challenging technical problems and doing impactful work you should join our team.

In this job you will be responsible for timing constraints development, STA and timing closure on  leading edge CMOS technologies and flows. This includes synthesis through place and route, timing closure, and tapeout signoff.

Responsibilities

• Drive the STA sign-off  for our flagship Silicon photonics chips at various technology nodes. 
• Analyze fab guidelines and work with the methodology team to incorporate sign off corners, margins, and derates into timing analysis flows and methodologies.
• Collaborate with the  architecture, RTL, and DFT teams to analyze the timing complexities and develop consolidated timing modes and constraints for synthesis, along with PnR and chip timing sign-off flows.
• Analyze and understand the tradeoffs between power/performance and area goals to drive them into overall chip implementation flows.
• Run full-chip STA and accurately project the timing summary across scenarios.
• Leverage Tempus/PrimeTime to automate timing ECO generation for effective closure and support physical design implementation.
• Document best practices and lessons learned to drive continuous improvements in future projects.

Qualifications:

• Bachelor’s degree in Electrical Engineering or Computer engineering
• 12 years of Physical Design experience, with a minimum of 5 years hands-on experience in ASIC STA and timing constraints development, timing closure with Cadence or Synopsys tools 
• Experience in driving timing closure by effectively managing on-chip variation derates, optimizing multi-mode multi-corner constraints, and implementing robust clock tree building strategies
• Well versed with scripting languages like TCL and Python, PERL, or Shell
• Strong problem solving skills with attention to every technical aspect
• Be a strong team player with clear and precise communication skills

Preferred Qualifications:

• Master’s degree in Electrical Engineering or Computer engineering
• A minimum of 8 years of hands-on experience in ASIC STA and timing constraints development, timing closure with Cadence or Synopsys tools 

As a Design Verification Engineer at Lightmatter, you will find yourself at the heart of a dynamic, interdisciplinary team. Your role will involve close collaboration with our digital design experts, using UVM testbench techniques to rigorously verify their designs. Your responsibilities will include working alongside photonic and analog designers, gaining a deep understanding of their innovative designs, and applying Real Number Modeling (RNM) and AMS verification methods. This critical function ensures the integrity of their work. We are hiring at multiple levels. 

Your interaction with the Architecture team will be crucial in comprehending system requirements and spearheading performance verification. This role offers a unique platform to enhance your skills across a spectrum of areas including UVM, AMS modeling, mixed-signal verification, post-silicon validation formal verification, emulation, and both performance modeling and verification.

Responsibilities

• Define and enhance the DV methodologies required for integrated digital, analog, and photonic devices with a strong emphasis on emulation for design verification.
• Create and execute test plans to ensure high-quality tapeouts that meet functional and performance goals, while leveraging emulation where appropriate.
• Collaborate with architects, DV engineers, digital designers, and analog/photonics designers to define validation flows.
• Create reusable and scalable test bench components that enable efficient and effective verification.
• Close coverage and finish all DV signoff requirements, with a focus on leveraging mixed signal simulations to achieve high coverage metrics
• Work on block level and full chip design verification.
• Integrate analog design IPs from vendors and internal teams and develop verification environments for simulation and emulation.
• Work with analog design engineers to create behavioral models for analog designs and with digital design engineers to integrate models/testcase/checkers into upper levels

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, a related field, or equivalent experience
• Minimum of 8 years of design verification and SystemVerilog experience
• 2+ years of experience in Python
• Expertise in developing with the UVM library
• Experience with simulators such as Xcelium, ModelSim, Questa, or VCS
• Strong problem solver and collaborator

Preferred Qualifications 

• Master’s degree or higher in Electrical Engineering, Computer Engineering, a related field, or equivalent experience with 6 years of relevant experience 
• Experience with post-silicon validation and debug
• Experience with AMS verification