About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

Etched is building a new category of AI hardware: frontier inference clusters. As a Physical Design Engineer, you will own block-level implementation from synthesis through GDSII sign-off. You will drive Block-level & Subsystem PPA Optimization, and collaborate closely with RTL designers to provide actionable feedback, ensuring we iterate at unprecedented speeds to bring our products to market.

Key Responsibilities

• Own block-level and/or subsystem physical design end to end, including floorplanning, synthesis, placement, clock tree synthesis, and routing through GDSII.

• Drive block-level timing closure across all corners and modes, including constraint development, STA debug, and functional and timing ECO implementation.

• Close block-level signoff across EM, IR drop, RC extraction and correlation, and physical verification (DRC, LVS, antenna).

• Generate abstracts, views, and timing budgets for clean hierarchical integration of your blocks into the top level.

• Collaborate with RTL Designers and provide Physical Design feedback to improve PPA.

• Continuously improve the PPA of owned blocks and contribute learnings back into the shared RTL-to-GDSII flow.

• Supervise physical design work outsourced to 3rd party services and be accountable for the quality and closure of delivered blocks.

You may be a good fit if you have

• 5-10+ years of previous experience with PD

• Tools, flow, and design methodology from RTL synthesis to GDSII sign-off

• Experience with back-end design and timing closure on advanced process nodes (5nm and below)

• Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows

• Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)

• Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis

• Scripting ability in Tcl, Python, or Perl for flow automation and debug

• Deeply creative and able to think from first principles

Strong candidates may also have experience with

• Familiarity with modern ML and LLM model architectures

• Ability to program with Python or another scripting language

• Familiarity with AI tools for programming/coding

• Startup experience or comfort working in fast-paced environments

Benefits

• Medical, dental, and vision packages with generous premium coverage

• $500 per month credit for waiving medical benefits

• Housing subsidy of $2k per month for those living within walking distance of the office

• Relocation support for those moving to San Jose (Santana Row)

• Various wellness benefits covering fitness, mental health, and more

• Daily lunch and dinner in our office

• Unlimited compute budget subject to ROI justification

How we’re different

Etched believes in the . We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.

We greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

This role is based in our Austin office, with regular time spent working alongside the team in San Jose. During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters to ramp quickly. After that, this shifts to roughly one week per month for ongoing collaboration.

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

At Etched, building and maintaining a secure yet friction-free computing environment is central to our mission. As a Security Engineer, you will protect the networks, systems, and applications that enable our engineers to push the limits of AI hardware. You will design, implement, and operate the monitoring, detection, and response infrastructure that safeguards Etched’s intellectual property, high-performance compute clusters, and developer workflows across both on-prem and cloud environments. You will partner with infrastructure, IT, application, and external provider teams to build systems that are secure by design, resilient under pressure, and seamless and easy to use for the end users.

This role combines hands-on technical depth with a focus on scalability and automation. You will take ownership of Etched’s security posture across infrastructure, IT, and applications, driving proactive threat detection, real-time monitoring, and rapid incident response. Your decisions will always balance maintaining full firm-wide velocity while improving our security and defense posture. You will develop tools, automation, and workflows that evolve with our rapidly growing and expanding footprint and ensure that security enhances, rather than hinders, innovation. If you are motivated by precision, ownership, and impact, you will find Etched the ideal place to advance your craft and contribute to the future of AI computing.

Key Responsibilities

• Manage and harden security baselines across on-prem, hybrid, and cloud systems, ensuring strong protection while maintaining speed and usability.

• Integrate telemetry, logging, tracing, and management of structured, semi-structured, and unstructured data across the entire environment to provide unified and comprehensive observability into infrastructure and application activity.

• Lead vulnerability management, patching, and configuration assurance programs to reduce exposure and maintain a consistent security posture.

• Partner with infrastructure, IT, and application teams to strengthen identity, access, and network security through Okta, Google Workspace, and FreeIPA.

• Implement and maintain zero-trust network architectures, SASE controls, CASB solutions, and conditional access policies that protect both users and data across environments to ensure full access and full control of our data and IP regardless of location or device.

• Operate and enhance security operations tooling, including SIEM, SOAR, and EDR/XDR platforms, to ensure comprehensive monitoring and rapid detection of threats.

• Develop and tune detection logic, automation, and playbooks for identifying and responding to threats such as insider activity, lateral movement, and anomalous behavior.

• Investigate and respond to security incidents, performing root-cause analysis, containment, and remediation while coordinating with engineering and IT.

• Build automation, scripts, AI agents, and integrations that streamline monitoring, alerting, and remediation workflows to improve efficiency and reliability.

• Establish metrics, dashboards, and feedback mechanisms to measure detection coverage, response time, and overall security health.

• Promote a culture of security awareness and ownership across engineering teams, ensuring that protection and productivity advance together.

Representative Projects

• Implementing a centralized security telemetry pipeline that aggregates logs and signals from networks, compute clusters, storage, endpoints devices, build systems, and cloud services into a unified SIEM for improved detection coverage.

• Designing and developing Security Orchestration, Automation, and Response (SOAR) workflows to automate repetitive tasks like alert triage, data gathering, and initial containment, which improves SOC efficiency.

• Help build a secure and flexible end user access framework that uses SDWAN, SASE, CASB, conditional access, EDR and XDR, and MDM/MAM to support productive, friction-free and secure work from any location using different devices.

• Network Security Monitoring: Configuring and monitoring network intrusion detection/prevention systems (IDS/IPS) and firewalls to detect anomalies in network traffic, especially on the SDWAN and client VPN links

• Creating and refining detailed, documented incident response plans and playbooks tailored to specific scenarios, such as a breach in a lab environment or a compromised silicon testing machine.

• Conducting regular vulnerability assessments and penetration testing on internal systems and applications, then coordinating with relevant teams to manage and remediate identified weaknesses.

You May Be a Good Fit If You Have

• 5-7+ years of experience in security engineering, SOC operations, detection engineering, incident response, or a similar role that blends hands-on technical work with analytical problem solving.

• Strong software engineering skills with Python, Go, Bash, (C and Rust a major plus), including the ability to design, implement, and maintain high-quality code, automation frameworks, services, and integrations that improve security, observability, and operational efficiency.

• Proficiency with SIEM and SOAR platforms, including experience building detections, dashboards, and automated workflows.

• Deep understanding of EDR and XDR platforms, endpoint security hardening, and telemetry collection across macOS, Linux, Windows, and server environments.

• Experience implementing or supporting zero trust architectures, including conditional access, SASE, CASB, and identity-driven access control models.

• Familiarity with IAM and SSO systems such as Okta, Google Workspace, and FreeIPA and the ability to design secure identity, access, and authentication policies.

• Strong networking knowledge, including SDWAN, VPN, IDS and IPS, firewall administration, segmentation strategy, and monitoring of network traffic for anomalies.

• Hands-on experience managing or building security telemetry pipelines, log ingestion frameworks, or observability systems that support both structured and unstructured data.

• Solid understanding of threat modeling, the MITRE ATT and CK framework, attacker tradecraft, and common detection and response patterns.

• Experience performing vulnerability assessments, penetration testing, or secure configuration reviews and collaborating with teams to remediate identified risks.

• Exposure to cloud and hybrid environments such as AWS, GCP, or on-prem clusters and the ability to evaluate risks and implement protective controls across these environments.

Benefits

• Full medical, dental, and vision packages, with generous premium coverage

• Housing subsidy of $2,000/month for those living within walking distance of the office

• Daily lunch and dinner in our office

• Relocation support for those moving to San Jose (Santana Row)

• Unlimited compute budget subject to ROI justification

How we’re different

Etched believes in the . We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.

We are based in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

• Co-Develop cutting-edge software optimized across hardware and software driving the full potential of very large AI models.

• Solve challenging problems across the full stack, from low-level drivers and APIs to high-level applications and frameworks.

• Contribute to the development of AI solutions that will revolutionize industries like natural language processing, chain of reasoning automation, generative media.

You may be a good fit if you have

• Bachelor's degree or equivalent practical experience.

• Experience in software development, and with data structures/algorithms.

• Experience developing and testing software on launching products.

• Experience with firmware design, implementation, and troubleshooting.

• Experience with embedded architectures, IO technologies (I2C, SPI, PCIe, DRAM etc.), as well as concepts like scalability, fault tolerance, and consistency.

Strong candidates may also have experience with (Nice-to-have qualifications)

• Master’s degree Computer Science, or a related technical field.

• Experience resolving customer-related issues.

• Experience solving ambiguous problems.

• Excellent verbal and written communication skills.

Benefits

• Medical, dental, and vision packages with generous premium coverage

  • $500 per month credit for waiving medical benefits

• Various wellness benefits covering fitness, mental health, and more

• Daily lunch + dinner in our office

• Unlimited compute budget subject to ROI justification

How we’re different

Etched believes in the . We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.

We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

This role is based in our Austin office, with regular time spent working alongside the team in San Jose. During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters to ramp quickly. After that, this shifts to roughly one week per month for ongoing collaboration.

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

We are seeking a Design Verification Engineer to join our Internal IP DV team. You will ensure the custom IPs powering our chips — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.

Key responsibilities

• Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems).

• Define and execute verification plans covering functional correctness, corner cases, concurrency, and performance bottlenecks.

• Debug complex datapath and protocol issues in RTL and testbench environments.

• Work closely with architects and designers to validate functionality and design intent.

• Partner with SW, FW, and emulation teams to ensure end-to-end bring-up and debug coverage.

• Contribute to reusable DV infrastructure, coverage models, and methodology improvements.

You may be a good fit if you have

• Proficiency with UVM and SystemVerilog.

• Strong debugging and problem-solving skills for complex digital designs.

• Solid knowledge of computer architecture and digital design fundamentals.

• Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics.

Strong candidates may also have experience with

• Familiarity with SystemVerilog Assertions (SVA) and formal verification techniques.

• Experience verifying systolic arrays, DMA engines, or NoC/AXI protocols.

• Scripting skills (Python/Perl/TCL or similar) for automation, debug and regression flows.

Benefits

• Medical, dental, and vision packages with generous premium coverage

  • $500 per month credit for waiving medical benefits

• Various wellness benefits covering fitness, mental health, and more

• Daily lunch + dinner in our office

• Unlimited compute budget subject to ROI justification

How we’re different

Etched believes in the . We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.

We greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

This role is based in our Austin office, with regular time spent working alongside the team in San Jose. During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters to ramp quickly. After that, this shifts to roughly one week per month for ongoing collaboration.

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

We are seeking a Design Verification Engineer to join our Systems/Performance Verification team. You will ensure the custom IPs powering our chips — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.

Key responsibilities

• Work closely with architects and RTL designers on verifying the performance features of the design and correlating with performance models (both pre-silicon and post-silicon).

• Work closely with software and application developers on identifying performance bottlenecks and tuning the software.

• Develop test plans and test infrastructure/tools for performance tuning, correlation, and verification.

• Improve and maintain the architectural performance models.

• Develop tests in SystemVerilog, Python, or vectors to debug and correlate the RTL and performance model.

• Develop SystemVerilog or Python-based checkers for verifying the performance features.

• Develop coverage monitors and analyze coverage to ensure all performance features are covered.

• Debug performance issues and conduct performance tuning on silicon.

• Drive end-to-end performance tuning, ensuring optimal hardware utilization, software efficiency, and architectural alignment across the ASIC design lifecycle.

You may be a good fit if you have

• Strong understanding of digital design, RTL, and ASIC design flows.

• Hands-on experience with performance verification, simulation, and modeling.

• Comfortable developing checkers, coverage monitors, and testbenches in SystemVerilog.

• Skilled in writing Python scripts for automation, data analysis, and performance modeling.

• Experience building and maintaining performance models for chip subsystems.

• Understanding of memory hierarchies, pipelines, interconnects, and compute accelerators.

• Familiarity with performance bottleneck analysis, compiler optimizations, and workload tuning

• Some exposure to kernel level performance metrics and profiling tools.
  

Benefits

• Medical, dental, and vision packages with generous premium coverage

  • $500 per month credit for waiving medical benefits

• Various wellness benefits covering fitness, mental health, and more

• Daily lunch + dinner in our office

• Unlimited compute budget subject to ROI justification

How we’re different

Etched believes in the . We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.

We greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

This role is based in our Austin office, with regular time spent working alongside the team in San Jose. During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters to ramp quickly. After that, this shifts to roughly one week per month for ongoing collaboration.

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

Etched is looking for exceptional Physical Design engineers to join our team. In this role, you
will own block-level implementation and verification, drive timing closure and PPA optimization, supervise 3rd party design work, and help improve our design flows and iteration speed.

Key Responsibilities

• Deeply understand what is involved in physical design

• Running PD flows to close blocks, support ASIC infrastructure, automate PD flows,
  improve CAD infrastructure

• Collaborate with RTL Designers and provide Physical Design feedback to improve PPA

• Drive dashboards that show the convergence of projects related to PD

• Optimize tool flows, working with EDA vendors to incorporate the latest features

• Accountable for block level closure

• Supervise the outsourcing of physical design to a 3rd party service

You may be a good fit if you have

• 5-10+ years of previous experience with PD

• Tools, flow, and design methodology from RTL synthesis to GDSII sign-off

• Experience with back-end design and timing closure on advanced process nodes (5nm
  and below)

• Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler)
  automated RTL-to-GDSII flows

• Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)

• Experience with UPF-based low power design methodology, power verification,synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS,
  routing, IR drop, and EM/antenna analysis

• Deeply creative and able to think from first principles

Strong candidates may also have experience with

• Familiarity with modern ML and LLM model architectures

• Ability to program with Python or another scripting language

• Familiarity with AI tools for programming/coding

• Startup experience or comfort working in fast-paced environments

Benefits

• Medical, dental, and vision packages with generous premium coverage

  • $500 per month credit for waiving medical benefits

• Various wellness benefits covering fitness, mental health, and more

• Daily lunch + dinner in our office

• Unlimited compute budget subject to ROI justification

How we’re different

Etched believes in the . We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.

We greatly value engineering skills. We do not have strict boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

This role is based in our Austin office, with regular time spent working alongside the team in San Jose. During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters to ramp quickly. After that, this shifts to roughly one week per month for ongoing collaboration.

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges.

Key responsibilities

• End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors

• Understand vendor IP configurations and handle handshake with internal IP team

• Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications.

• Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture.

• Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios.

You may be a good fit if you have

• 5+ years of design verification experience

• You enjoy digging deep into complex verification challenges and finding creative ways to expose corner-case bugs.

• You have hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM and understand how to build scalable, reusable testbenches.

• You are comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs.

• You thrive in a fast-paced startup environment and can take ownership of projects with minimal direction.

• You collaborate naturally with cross-functional teams — from RTL design to software and emulation — and can clearly communicate technical insights.
  

Strong candidates may also have experience with

• Experience handling vendors and integration of IP/VIP’s

• UVM/System Verilog

Benefits

• Medical, dental, and vision packages with generous premium coverage

  • $500 per month credit for waiving medical benefits

• Various wellness benefits covering fitness, mental health, and more

• Daily lunch + dinner in our office

• Unlimited compute budget subject to ROI justification

How we’re different

Etched believes in the . We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.

We greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

This role is based in our Austin office, with regular time spent working alongside the team in San Jose. During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters to ramp quickly. After that, this shifts to roughly one week per month for ongoing collaboration.