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Intel Foundry Overlay Development Engineer
Intel · USA - OR - Hillsboro, United States of America
$156k–255k
31 days ago
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Senior Laser Designer
Intel · USA - CA - Santa Clara, United States of America
$164k–312k
31 days ago
♡
CPU Physical Design Engineer
Intel · USA - TX - Austin, United States of America
$106k–149k
31 days ago
♡
Silicon Photonics Wafer Test Automation Development Engineer
Intel · US, California, Santa Clara
$150k–245k
31 days ago
♡
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Intel Foundry Overlay Development Engineer
Intel · USA - OR - Hillsboro, United States of America
Pay
$156k–255k
Setting
On-site
Job Details: Job Description: Embark with us on a journey of growth and transformation as we create exceptionally engineered technology and bring AI everywhere. As a valued team member, your adaptability and attention to detail will contribute to our drive for results and relentless pursuit of quality, ensuring we meet our customers' needs with precision. Join us and build on our legacy of innovation and collaboration as we deliver world‑changing technology that improves the life of every person on the planet. Life at Intel: https://jobs.intel.com/en/life-at-intel This position is in the Logic Technology Development team working in one of the most advanced semiconductor process technologies in the world. You will design, execute, and analyze cutting edge experiments to develop the process of the next technologies to come into the market. Come join us and help shape the future of the semiconductor process for decades to come. What we offer: We foster a collaborative, supportive, and exciting environment where the brightest minds in the world come together to achieve exceptional results. We give you opportunities to transform technology and create a better future by delivering products. We provide benefits that promote a healthy, enjoyable life: excellent medical plans, wellness programs, and amenities, time off, recreational activities, discounts on various products and services, and many more creative perks that make Intel a Great Place to Work. What we do: The Logic Technology Development (LTD) organization delivers the latest process technology innovations to drive Intel's amazing product roadmap. What you will be considered for: LTD Module Development Engineers are responsible for leading scientific research enabling the manufacture of innovative device architectures but not limited to: Lead scientific research enabling the manufacture of innovative device architectures coupled with the realization of these architectures. Designing, executing, and analyzing experiments necessary to meet engineering specifications for their process. Participate in the development of intellectual property. Integrate the many individual steps necessary for the manufacture of complex microprocessors. Ramp to manufacturing volumes to demonstrate the technology meets requirements while simultaneously transferring the technology to counterparts in manufacturing via the Copy Exactly Methodology. The successful candidate must demonstrate: Strong communication skills and the ability to work effectively in cross-functional development teams. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. The requirements listed would be obtained through a combination of industry-relevant job experience, internship experience, and/or classes/research, and post-doctoral research. Minimum Qualifications – What You Bring Education: Bachelor's degree with 12+ years, Master's degree with 10+ years, or Ph.D. with 7+ years of experience in Materials Science, Chemical Engineering, Chemistry, Physics, Mechanical Engineering, Electrical Engineering, or a related STEM discipline. 7+ years of hands-on lithography industry experience. Current experience in advanced node overlay development processes. Proven ability to troubleshoot process impacts on overlay mark performance. Experience with integrated process development to co-optimize process flows and overlay mark design. Demonstrated proficiency in Design of Experiments (DOE), Statistical Process Control (SPC), and data analysis. Preferred Qualifications — Where Your Background Shines Experience driving integrated process change methodologies based on overlay impact analysis. Direct overlay equipment development experience and vendor engagement. Hands-on experience with ASML EUV and DUV scanner platforms. Strong capability to troubleshoot complex process and production issues at advanced nodes. Deep working knowledge of lithography equipment operation, including automation and process control systems. Familiarity with factory automation or manufacturing execution and control systems. We invite you to bring your skills, ideas, and aspirations to Intel, where you will find the perfect environment to grow and make an impact. Apply today to become part of a team that shapes the future of workplace and real estate services. Join us in advancing memory systems technology and delivering innovative solutions that will shape the future of computing. Interview Tips: https://www.intel.com/content/www/us/en/jobs/hiring.html Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $155,520.00-255,200.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. Intel’s official careers website. Find your next job and take on projects that shape tomorrow’s technology. Benefits Internships Life at Intel Locations Recruitment Process
Listed by Intel for a position based in the United States. Employers on this board attest they are hiring domestically.
Senior Laser Designer
Intel · USA - CA - Santa Clara, United States of America
Pay
$164k–312k
Setting
On-site
Job Details: Job Description: The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. The Role and Impact As a Senior Laser Designer, you will play a pivotal role in developing advanced photonics components and integrating them into Silicon Photonic circuits to drive next-generation optical communication solutions. Your daily responsibilities will include designing, simulating, and optimizing DFB lasers while advancing methodologies for performance validation and reliability testing. Your contributions will have a direct impact on Intel's ability to deliver cutting-edge technology in data centers and AI applications. Business Group Intel's Integrated Photonics Solutions (IPS) team leads the industry in silicon photonics integration, focusing on scalable high-volume manufacturing and delivering transformative bandwidth and speed for data centers. As part of this innovative group, you will help design and develop photonics components that support Intel's broader commitment to driving technological advancements and enabling future growth in optical communications. Key Responsibilities Design, simulate, and optimize DFB lasers for high-speed optical communication applications. Perform tolerance analysis to enhance device performance, power efficiency, and reliability. Lead test chip execution, including design layout, tapeout, validation, and data analysis. Develop and refine photonic modeling methodologies and propose new testing approaches. Conduct research in emerging photonic technologies to define next-generation architectures and initiate intellectual property development programs. Analyze test data from component characterizations to identify performance gaps and implement improvement strategies. Collaborate with interdisciplinary engineering teams to ensure seamless integration of photonics components into system-level designs. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences. Minimum Qualifications: Master's degree in a relevant field such as Electrical Engineering, Physics, or a related discipline with 6+ years of relevant experience OR Ph.D. with 4+ years of industry expertise. Extensive experience in designing and simulating DFB lasers including InP epi design. Industrial experience developing DFB lases in high volume manufacturing, including taking designs through product qualification. Preferred Qualifications: Project leadership experience. Expertise in analyzing photonic component or integrated circuit (PIC) test data using statistical tools such as JMP or data libraries in MATLAB/Python. Matlab programing experience Familiarity with industry-standard layout tools like Cadence and KLayout for component design and test chip execution. System-level modeling expertise for optimizing optical link performance and scalability. Published research in peer-reviewed journals focused on photonics technologies. We are seeking driven innovators passionate about shaping the future of photonics technology. If you are excited to contribute to cutting-edge advancements in silicon photonics, we encourage you to apply and explore the opportunity to join our team. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $164,470.00-311,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. Intel’s official careers website. Find your next job and take on projects that shape tomorrow’s technology. Benefits Internships Life at Intel Locations Recruitment Process
Listed by Intel for a position based in the United States. Employers on this board attest they are hiring domestically.
Packaging Module Development Engineer
Intel · US, Arizona, Phoenix
Pay
$134k–189k
Setting
On-site
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locations
US, Arizona, Phoenix
time type
Full time
posted on
Posted 10 Days Ago
time left to apply
End Date: November 6, 2026 (30+ days left to apply)
job requisition id
JR0286214
Job Details:
Job Description:
The Advanced Packaging Technology and Manufacturing (APTM) organization is seeking a Metrology Equipment Engineer to drive process control, manufacturing data analytics, and yield improvement for Thermal Compression Bonding (TCB) technologies.
The successful candidate develops and sustains metrology systems, measurement methods, and inspection equipment to support Intel’s roadmap for advanced packaging and Thermal Compression Bonding technologies. They apply engineering principles and novel concepts to deliver measurement solutions that improve process control, product quality, reliability, productivity, yield, and manufacturability.
Key Responsibilities
Optimizes metrology capability across laboratory and manufacturing environments by developing and qualifying measurement processes, equipment specifications, calibration methods, and correlation techniques.
Uses design of experiments, statistical analysis, and measurement system analysis to improve repeatability, reproducibility, and consistency across tools, sites, and product generations. Documents technical findings and improvements through white papers, reports, and qualification summaries.
Establishes measurement specifications and collaborates with equipment suppliers, internal development teams, quality, process, and manufacturing organizations to ensure measurement capability, traceability, and data integrity meet program needs.
Provides technical consultation on measurement challenges, equipment issues, lab-to-factory correlation, and metrology process improvements.
Supports standardization of metrology methods, and works closely with packaging technology development, process engineering, and partner engineering groups to assess readiness and meet product milestones.
Qualifications:
You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
Bachelor's degree with 4+ years or Master's degree with 3+ years, or PhD with 1+ years of relevant experience in Electrical Engineering, Mechanical Engineering, Physics, Metrology, Instrumentation, Optical Engineering, or a related engineering discipline.
1+ years of Hands-on experience in metrology systems development, measurement equipment qualification, calibration, and/or measurement method development in a manufacturing, lab, or engineering environment.
2+ years of knowledge of measurement system analysis (MSA), including bias, linearity, stability, repeatability, and reproducibility.
2+ years of experience with electrical measurements and test, such as continuity, resistance, leakage, signal integrity basics, or related parametric test methods.
2+ year of experience with optical metrology, including microscopes, imaging systems, inspection methods, and/or machine vision.
2+ years of working knowledge of data analysis tools such as Python, Excel, SQL, or similar tools for measurement analysis and reporting.
Preferred Qualifications
Experience in semiconductor manufacturing, preferably in advanced packaging.
Experience developing or sustaining metrology systems for process control, product qualification, or reliability evaluation.
Strong background in equipment selection, tool qualification, acceptance testing, and calibration traceability.
Experience with machine vision systems, automated inspection, or camera-based measurement techniques.
Familiarity with lab-to-factory correlation, tool matching, and cross-tool measurement agreement studies.
Experience with DOE, correlation analysis, and method optimization for metrology or test systems.
Knowledge of quality systems, measurement documentation, and standardization of metrology methods.
Experience working with suppliers, vendors, or external calibration/measurement service providers.
Demonstrated ability to analyze measurement data using statistical methods to identify variation, correlation issues, tool drift, and root causes.
Join us at Intel to contribute to technological advancements while building a rewarding and impactful career. Apply now to be a part of our extraordinary journey.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Arizona, Phoenix
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $133,800.00-188,890.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
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Listed by Intel for a position based in the United States. Employers on this board attest they are hiring domestically.
AI Infrastructure Engineer
Intel · US, California, Santa Clara
Pay
$170k–315k
Setting
On-site
Listed by Intel for a position based in the United States. Employers on this board attest they are hiring domestically.
CPU Physical Design Engineer
Intel · USA - TX - Austin, United States of America
Pay
$106k–149k
Setting
On-site
Job Details: Job Description: Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Life at Intel As a member of Intel's CPU development team, you will have a front seat in designing the latest core IP to power cutting edge compute processors across client, server, and AI fields. We innovate state of the art microprocessor architecture on the most advanced and latest process technologies with a focus on power efficiency. Our core designs are present in nearly all segments of Intel's compute roadmap. Job responsibilities include but are not limited to: Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams. Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT. Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU. Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications: Bachelors in Computer Engineering or Electrical Engineering or related field with 2+ years of relevant work experience or M.S. in Computer Engineering or Electrical Engineering or related field (or higher degree) with 1+ years of relevant work experience. 1+ years' experience in Synthesis of a digital logic block or partition. 1+ years of experience in each of the following (may be obtained through coursework and/or internship): Integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure. PV convergence (such as static timing and power analysis). Chip physical design verification including formal equivalence, electrical rules, DRC/LVS, and Noise flow. TCL Scripting. Preferred Qualifications: Master's Degree in Computer Engineering or Electrical Engineering or related field. Knowledge with Physical design best known practices concerning floor-planning, routing techniques, clock distribution. At least 1 Completion of Tape Out on advanced technologies. Knowledge of Static Timing Analysis, Noise analysis, and reliability verification techniques. Knowledge of RTL to GDS methodologies and formal equivalence Experience performing CPU level timing analysis and optimization, ensuring designs meet functional and performance requirements. Experience generating and verifying timing constraints while addressing timing violations at the chip or block level for CPU cores. Experience working closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning. Benefits at Intel Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion. Job Type: College Grad Shift: Shift 1 (United States of America) Primary Location: US, Texas, Austin Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $105,650.00-149,150.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. Intel’s official careers website. Find your next job and take on projects that shape tomorrow’s technology. Benefits Internships Life at Intel Locations Recruitment Process
Listed by Intel for a position based in the United States. Employers on this board attest they are hiring domestically.
Senior Laser and SOA Designer
Intel · US, California, Santa Clara
Pay
$142k–269k
Setting
On-site
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Senior Laser and SOA Designer
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locations
US, California, Santa Clara
time type
Full time
posted on
Posted 8 Days Ago
job requisition id
JR0286237
Job Details:
Job Description:
The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives.
The Role and Impact
As a Senior Laser Designer, you will play a pivotal role in the simulation, design, and development of advanced photonics components such as lasers, and semiconductor optical amplifiers. You will be responsible for designing and optimizing photonics components to enhance system performance, reliability, and integration into next-generation technologies. This position offers a unique opportunity to contribute directly to the development of cutting-edge solutions for data centers and AI applications.
Business group
You will join Intel's Integrated Photonics Solutions (IPS) Group, a global leader in silicon photonics integration and commercialization. This innovative team focuses on developing and scaling high-performance optical solutions to enable future data center and AI bandwidth growth. By leveraging world-class research and development, IPS drives advancements in optical communication technologies to support Intel's broader vision of delivering transformative solutions to the industry.
Key Responsibilities
Design, simulate, and develop photonics components such as DFB lasers, and semiconductor optical amplifiers.
Perform tolerance analysis and optimize components for performance, power efficiency, area, and reliability.
Collaborate with interdisciplinary engineering teams to ensure seamless integration of photonics components into system-level designs.
Drive test chip execution, including chip design, layout, tape-out, test, and validation.
Analyze test data from photonics component characterizations, identify performance gaps, and propose improvement strategies.
Develop and implement advanced photonics component and system modeling methodologies.
Lead research initiatives on novel photonics technologies, including next-generation component architectures and intellectual property development.
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.
Minimum Qualifications
Master's degree in Electrical Engineering, Physics, Optical Science, or related fields with 3+ years of relevant experience OR Ph.D. with 1+ years of relevant experience.
Proven expertise in designing, simulating, and analyzing photonics components including DFB lasers and semiconductor optical amplifiers.
Preferred Qualifications:
Expertise in analyzing photonic component or integrated circuit (PIC) test data using statistical tools such as JMP or data libraries in MATLAB/Python.
Matlab programing experience
Familiarity with industry-standard layout tools like Cadence and KLayout for component design and test chip execution.
System-level modeling expertise for optimizing optical link performance and scalability.
Published research in peer-reviewed journals focused on photonics technologies.
Join us to explore the boundaries of photonics technology and make an impact on the future of high-speed communication and data center innovations. Be part of a talented team dedicated to driving transformation in optical solutions and shaping the next generation of connectivity.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Santa Clara
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
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About Us
Intel’s official careers website. Find your next job and take on projects that shape tomorrow’s technology.
Discover your place in our world-changing work
Benefits
Internships
Life at Intel
Locations
Recruitment Process
Three recognitions. One Intel. We're proud to be named to:
Follow Us
Intel Privacy Notice & Legal Statements
© 2026 Workday, Inc. All rights reserved.
Listed by Intel for a position based in the United States. Employers on this board attest they are hiring domestically.
Silicon Photonics Wafer Test Automation Development Engineer
Intel · US, California, Santa Clara
Pay
$150k–245k
Setting
On-site
Skip to main content
Welcome!
Intel Corporation uses cookies and similar technologies on this website to improve your online experience, to analyze site usage and to show tailored advertising to you. For more information, visit our Cookie Notice.
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Silicon Photonics Wafer Test Automation Development Engineer
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locations
US, California, Santa Clara
time type
Full time
posted on
Posted 10 Days Ago
job requisition id
JR0286239
Job Details:
Job Description:
The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives.
Intel's Integrated Photonics Solutions (IPS) organization is driving the future of high-performance computing and networking through the development of advanced optical interconnect technologies built on Intel's silicon photonics platform. We are seeking a highly motivated Silicon Photonics Wafer Test Automation Development Engineer to support the development, implementation, and optimization of wafer-level testing solutions for integrated photonic devices.
Key Responsibilities:
Lead the design, development, and maintenance of automated wafer-level test systems for silicon photonics devices, including optical coupling systems, wafer probing solutions, automation frameworks, and test software.
Develop and maintain software applications to support automated characterization and production testing of photonic integrated circuits (PICs) and optical components.
Collaborate closely with photonic device designers to implement and validate test algorithms that accurately characterize device performance.
Partner with data engineering and analytics teams to ensure test outputs meet data quality, processing, and reporting requirements.
Create, update, and maintain test procedures, specifications, and documentation while providing training and technical guidance to technicians.
Work with laboratory technicians to monitor, troubleshoot, and improve test system performance, reliability, and throughput.
Drive effective cross-functional collaboration with design, manufacturing, process integration, and quality teams to support product development and production goals.
Demonstrate strong teamwork, communication, and organizational skills while managing multiple tasks in a dynamic, fast-paced environment.
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.
Minimum Qualifications
• Bachelor's degree in Electrical Engineering, Physics, Materials Science, or a related technical discipline & 4+ years of experience OR a Master's degree in Electrical Engineering, Physics, Materials Science, or a related technical discipline & 3+ years of experience.
• 4+ years of hands-on experience with semiconductor device characterization and testing methodologies.
• 4+ years of experience designing and developing automated test solutions for engineering or manufacturing environments.
• 2+ years of experience in software development using Microsoft Windows (MS Visual Studio is a plus).
Preferred Qualifications:
• Ph.D. in Electrical Engineering, Physics, Optical Engineering, Materials Science, or a related field.
• Experience testing and characterizing integrated photonic devices and/or photonic integrated circuits.
• Strong understanding of optical component design, characterization, and measurement techniques.
• Experience operating wafer probing equipment and automated wafer-level test platforms.
• Familiarity with National Instruments (NI) hardware, drivers, and remote instrument control protocols.
• Experience with mechanical system design and integration.
• Background in optical system design and alignment.
• Experience in RF test.
• Solid understanding of software development lifecycle (SDLC), software architecture, and best practices for maintainable test software development.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Santa Clara
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $149,600.00-245,160.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
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Listed by Intel for a position based in the United States. Employers on this board attest they are hiring domestically.
Simulation and Modeling Lead
Intel · US, Oregon, Hillsboro
Pay
$174k–285k
Setting
On-site
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locations
US, Oregon, Hillsboro
time type
Full time
posted on
Posted 11 Days Ago
job requisition id
JR0285459
Job Details:
Job Description:
In this role, you will lead cross-functional collaboration to advance circuit simulation and modeling capabilities for advanced foundry technologies.
Your responsibilities will include:
Vendor collaboration: Partnering with EDA vendors to enhance and validate industry-standard simulation tools and design flows.
Technology alignment: Working closely with technology leaders, VLSI physical design teams, and PDK teams to ensure simulation and modeling capabilities are aligned with roadmap needs.
PDK readiness: Driving readiness of high quality simulation and modeling solutions so they are available in time for PDK delivery.
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Bachelor’s degree in electrical engineering or computer engineering or related engineering discipline with 12+ years or master’s degree in electrical engineering or a related discipline and at least 10 years of industry experience in the semiconductor field; or Ph.D. in Electrical Engineering or a related discipline with a minimum of 8 years of industry experience in the semiconductor field.
5+ years supporting circuit simulation tools and working with circuit simulation vendors to develop solutions.
5+ years collaborating with EDA vendors on optimizing circuit simulation and modeling for advanced technology nodes.
3+ years of hands-on experience with BSIM or other compact models for transistor modeling at advanced nodes (e.g., FinFET, GAA).
5+ years of comprehensive understanding of compact modeling, simulation methodologies used by digital and analog designers, aging modeling and methodologies and modeling interfaces to simulation tools like OMI.
Preferred Qualifications
Demonstrated experience in technical leadership and Proven capability to collaborate across multiple teams and geographies.
5+ years of experience in leading technical teams in the areas of simulation and modeling.
Exceptional leadership skills with focus on collaboration and finding solutions.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $173,660.00-284,580.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
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About Us
Intel’s official careers website. Find your next job and take on projects that shape tomorrow’s technology.
Discover your place in our world-changing work
Benefits
Internships
Life at Intel
Locations
Recruitment Process
Three recognitions. One Intel. We're proud to be named to:
Follow Us
Intel Privacy Notice & Legal Statements
© 2026 Workday, Inc. All rights reserved.
Listed by Intel for a position based in the United States. Employers on this board attest they are hiring domestically.
CPU Physical Design Engineer
Intel · USA - TX - Austin, United States of America
Pay
$106k–200k
Setting
On-site
Job Details: Job Description: Job Description Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Life at Intel As a member of Intel's CPU development team, you will have a front seat in designing the latest core IP to power cutting edge compute processors across client, server, AI fields. We innovate state of the art microprocessor architecture on the most advanced and latest process technologies with a focus on power efficiency. Our core designs are present in nearly all segments of Intel's compute roadmap. Job responsibilities include but are not limited to: Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams. Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT. Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU. Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications: Bachelors in Computer Engineering or Electrical Engineering or related field with 3+ years of relevant work experience or M.S. in Computer Engineering or Electrical Engineering or related field (or higher degree) with 2+ years of relevant work experience. 2+ years' experience in Synthesis of a digital logic block or partition. 2+ years of experience in each of the following: Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure. PV convergence (such as static timing and power analysis). Chip physical design verification including formal equivalence, electrical rules, DRC/LVS, and Noise flow. TCL Scripting. Preferred Qualifications: Prior work of sole responsibility for a CPU block synthesis and PNR. Knowledge with Physical design best known practices concerning floor-planning, routing techniques, clock distribution. At least 1 Completion of Tape Out on advanced technologies. Knowledge of Static Timing Analysis, Noise analysis, and reliability verification techniques. Knowledge of RTL to GDS methodologies and formal equivalence Experience performing CPU level timing analysis and optimization, ensuring designs meet functional and performance requirements. Experience generating and verifying timing constraints while addressing timing violations at the chip or block level for CPU cores. Experience working closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning. Benefits at Intel Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Texas, Austin Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $105,650.00-200,340.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. Intel’s official careers website. Find your next job and take on projects that shape tomorrow’s technology. Benefits Internships Life at Intel Locations Recruitment Process
Listed by Intel for a position based in the United States. Employers on this board attest they are hiring domestically.
CPU Verification Engineer
Intel · US, Texas, Austin
Pay
$106k–200k
Setting
On-site
Skip to main content
Welcome!
Intel Corporation uses cookies and similar technologies on this website to improve your online experience, to analyze site usage and to show tailored advertising to you. For more information, visit our Cookie Notice.
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